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? semiconductor components industries, llc, 2015 september, 2015 ? rev. 0 1 publication order number: noip1sn025ka/d noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka python 25k/16k/12k/10k global shutter cmos image sensors features ? a pin-compatible family with multiple resolutions: ? 25k = 5120 x 5120 active pixels ? 16k = 4096 x 4096 active pixels ? 12k = 4096 x 3072 active pixels ? 10k = 3840 x 2896 active pixels ? 4.5 m x 4.5 m low noise global shutter pixels with in-pixel correlated double sampling (cds) ? aps?h optical format (32.6 mm diagonal) for 25k ? monochrome (sn), color (se) and nir (fn) ? random programmable region of interest (roi) readout ? pipelined and triggered global shutter ? on-chip fixed pattern noise (fpn) correction ? 10-bit analog-to-digital converter (adc) ? 32 low-voltage differential signaling (lvds) high-speed serial outputs ? serial peripheral interface (spi) ? high-speed: 80 frames per second (fps) at 25 mpix ? 4.6 w power dissipation at full resolution, x32 lvds mode ? operational range: ?40 c to +85 c ? 355-pin pga package ? these devices are pb?free and are rohs compliant applications ? machine vision ? motion monitoring ? intelligent traffic systems (its) ? pick and place machines ? inspection ? metrology descriptio n the python xk family of cmos image sensors provide high resolution with very high bandwidth (up to 80 frame per second readout for 25 megapixel readout) in a pin?compatible family of devices. the high sensitivity 4.5 m pixels support both pipelined and triggered global shutter readout modes. the sensor also supports correlated double sampling (cds) readout in global shutter mode, reducing noise and increasing dynamic range. the sensor is programmed using a four?wire serial peripheral interface. black level can be calibrated automatically, or adjusted using a user programmable offset. the sensor also supports readout of up to 32 separate regions of interest (roi) to increase frame rate. image data is accessed through 32, 16, 8, or 4 lvds channels, each running at 720 mbps, and a separate synchronization channel is provided to facilitate image reconstruction. the python xk family is packaged in a 355-pin pga package and is available in a monochrome, bayer color, and extended near?infrared (nir) configurations. www.onsemi.com figure 1. python xk photograph
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 2 ordering information part number family description package product status noip1sn025ka-gdi python 25k 25 megapixel, lvds mono micro lens 355?pin pga production noip1se025ka-gdi 25 megapixel, lvds color micro lens noip1fn025ka-gdi 25 megapixel, lvds mono micro lens, nir noip1sn016ka-gdi python 16k 16 megapixel, lvds mono micro lens noip1se016ka-gdi 16 megapixel, lvds color micro lens noip1fn016ka-gdi 16 megapixel, lvds mono micro lens, nir noip1sn012ka-gdi python 12k 12 megapixel, lvds mono micro lens NOIP1SE012KA-GDI 12 megapixel, lvds color micro lens noip1fn012ka-gdi 12 megapixel, lvds mono micro lens, nir noip1sn010ka-gdi python 10k 10 megapixel, lvds mono micro lens noip1se010ka-gdi 10 megapixel, lvds color micro lens noip1fn010ka-gdi 10 megapixel, lvds mono micro lens, nir the p1?sn/se/fn base part is used to reference the mono, color and nir enhanced versions of the lvds interface. more details on the part number coding can be found at http://www.onsemi.com/pub_link/collateral/tnd310?d.pdf package mark side 1 near pin 1: noip1xx0rrka?gdi where xx denotes mono micro lens (sn) or color micro lens (se) or nir mono micro lens (fn), rr is the resolution of the sensor in mp (25, 16, 12 or 10) side 2: awlyyww, where awl is production lot traceability, and yyww is the 4?digit date code
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 3 specifications key specifications table 1. general specifications parameter specification pixel type global shutter pixel architecture shutter type pipelined and triggered global shutter optical format 25k: aps?h 16k: aps?h 12k: 4/3? 10k: 4/3? frame rate at full resolution 80 frames per second @ 25k 120 frames per second @ 16k 160 frames per second @ 12k 175 frames per second @ 10k master clock 360 mhz windowing 32 randomly programmable windows. normal, sub-sampled and binned readout modes adc resolution (note 1) 10-bit lvds outputs 32 data + 1 sync + 1 clock data rate 32 x 720 mbps power consumption 4.6 w package type 355 pga color rgb color, mono 1. the adc is 1 1-bit, down-scaled to 10-bit. the python xk uses a larger word-length internally to provide 10-bit on the output. table 2. electro?optical specifications parameter specification active pixels 25k: 5120 (h) x 5120 (v) 16k: 4096 (h) x 4096 (v) 12k: 4096 (h) x 3072 (v) 10k: 3840 (h) x 2896 (v) pixel size 4.5 m x 4.5 m conversion gain 0.085 lsb10/e - , 130 v/e - temporal noise < 14 e - (non?zero rot, 1x gain) responsivity at 550 nm 5.8 v/lux.s parasitic light sensitivity (pls) < 1/5000 full well charge > 12000 e - quantum efficiency (qe) x ff 50% at 550 nm pixel fpn (note 2) < 0.9 lsb10 prnu (note 2) < 1% mtf 68% @ 535 nm ? x?dir & y?dir 68% @ 535 nm ? x?dir & y?dir (nir) psnl @ 20 c (t_int = 30 ms) 91 lsb10/s, 1100 e - /s dark signal @ 20 c 3.9 e - /s, 0.33 lsb10/s dynamic range 59 db signal-to-noise ratio (snr max) 41 db 2. only includes high?frequency component
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 4 table 3. recommended operating ratings (note 3) symbol description min max units t j operating temperature range ?40 +85 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 4. absolute maximum ratings (note 4) symbol parameter min max units abs (1.0 v supply) abs rating for 1.0 v supply ?0.5 1.2 v abs (1.8 v supply group) abs rating for 1.8 v supply group ?0.5 2.2 v abs (3.3 v supply group) abs rating for 3.3 v supply group ?0.5 4.3 v abs (4.2 v supply) abs rating for 4.2 v supply ?0.5 4.6 v abs (4.5 v supply) abs rating for 4.5 v supply ?0.5 5.0 v t s (notes 4 and 5) abs storage temperature range 0 150 c abs storage humidity range at 85 c 85 %rh electrostatic discharge (esd) (notes 3 and 4) human body model (hbm): js?001?2010 2000 v charged device model (cdm): jesd22?c101 500 lu latch-up: jesd?78 140 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 3. operating ratings are conditions in which operation of the device is intended to be functional. 4. on semiconductor recommends that customers become familiar with, and follow the procedures in jedec standard jesd625?a. refer to application note an52561. long term exposure toward the maximum storage temperature will accelerate color filter degradation . 5. caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. the glass lid glue is permeable and can absorb moisture if the sensor is placed in a high % rh environment. table 5. electrical specifications boldface limits apply for t j = t min to t max , all other limits t j = +30 c (notes 6, 7, 8 and 9) parameter description min typ max units power supply parameters vdda_33 analog supply - 3.3 v domain. gnda_33 is connected to substrate 3.2 3.3 3.4 v idda_33 current consumption from analog supply 910 ma vddd_33 digital supply - 3.3 v domain. gndd_33 is connected to substrate 3.2 3.3 3.4 v iddd_33 current consumption from 3.3 v digital supply 90 ma vdd_18 digital supply - 1.8 v domain. gndd_18 is connected to substrate 1.7 1.8 1.9 v idd_18 current consumption 1.8 v digital supply 540 ma vdd_pix pixel array supply 3.25 3.3 3.35 v idd_pix current consumption from pixel supply 115 ma vdd_resfd floating diffusion reset supply 4.2 v gnd_resfd floating diffusion reset ground. not connected to substrate note this is a sinking power supply with 200 ma range. 0 v vdd_trans pixel transfer supply 3.3 v gnd_trans pixel transfer ground. not connected to substrate. note this is a sinking power supply with 200 ma range. 0 v 6. all parameters are characterized for dc conditions after thermal equilibrium is established. 7. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is r ecommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high?imped ance circuit. 8. minimum and maximum limits are guaranteed through test and design. 9. vref_colmux supply should be able to source and sink current
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 5 table 5. electrical specifications boldface limits apply for t j = t min to t max , all other limits t j = +30 c (notes 6, 7, 8 and 9) parameter units max typ min description vdd_calib pixel calibration supply 4.2 v gnd_calib pixel calibration ground. not connected to substrate 0 v vdd_sel pixel select supply 4.2 v gnd_sel pixel select ground. not connected to substrate. 0 0 0 v vdd_casc cascode supply 1.0 v vref_colmux [9] column multiplexer reference supply 1.0 v gnd_colbias column biasing ground. dedicated ground signal for pixel biasing. connected to substrate 0 v gnd_colpc column precharge ground. dedicated ground signal for pixel biasing. not connected to substrate 0 v ptot total power consumption 4600 mw popt power consumption at lower pixel rates configurable i/o - lvds (eia/tia-644): conforming to standard/additional specifications and deviations listed fserdata data rate on data channels ddr signaling - 32 data channels, 1 synchronization channel 720 mbps fserclock clock rate of output clock clock output for mesochronous signaling 360 mhz vicm lvds input common mode level 0.3 1.25 2.2 v tccsk channel to channel skew (training pattern allows per-channel skew correction) 50 ps lvds electrical/interface fin input clock rate 360 mhz tidc input clock duty cycle 45 50 55 % tj input clock jitter 20 ps fspi spi clock rate 10 mhz ratspi 10-bit (32 lvds channels): ratio: fin/fspi 30 10-bit (16 lvds channels): ratio: fin/fspi 60 10-bit (8 lvds channels): ratio: fin/fspi 120 10-bit (4 lvds channels): ratio: fin/fspi 240 6. all parameters are characterized for dc conditions after thermal equilibrium is established. 7. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is r ecommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high?imped ance circuit. 8. minimum and maximum limits are guaranteed through test and design. 9. vref_colmux supply should be able to source and sink current
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 6 table 5. electrical specifications boldface limits apply for t j = t min to t max , all other limits t j = +30 c (notes 6, 7, 8 and 9) parameter units max typ min description sensor requirements fot frame overhead time 50 s rot row overhead time 1 s fpix pixel rate (32 channels at 72 mpix/s) 2304 mpix/s frame specifications typical max units non?zero rot zero rot fps_roi1 xres x yres = 5120 x 5120 47 80 fps fps_roi2 xres x yres = 4096 x 4096 65 120 fps fps_roi3 xres x yres = 4096 x 3072 85 160 fps fps_roi4 xres x yres = 3840 x 2896 95 175 fps fps_roi5 xres x yres = 3840 x 2160 125 235 fps fps_roi6 xres x yres = 2880 x 2896 105 175 fps fps_roi7 xres x yres = 2048 x 2048 170 250 fps fpix pixel rate (32 channels at 72 mpix/s) 2304 mpix/s 6. all parameters are characterized for dc conditions after thermal equilibrium is established. 7. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is r ecommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high?imped ance circuit. 8. minimum and maximum limits are guaranteed through test and design. 9. vref_colmux supply should be able to source and sink current disclaimer : image sensor products and specifications are subject to change without notice. products are warranted to meet the production data sheet and acceptance criteria specifications only. color filter array the python xk color sensor is processed with a bayer rgb color pattern as shown in figure 2. pixel (0,0) has a red filter situated to the bottom left. green1 and green2 have a slightly dif ferent spectral response due to (optical) cross talk from neighboring pixels. green1 pixels are located on a green-red row, green2 pixels are located on a blue-green row. figure 2. color filter array for the pixel array pixel (0;0) y x
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 7 quantum efficiency figure 3. quantum efficiency curve for mono and color 0 10 20 30 40 50 60 300 400 500 600 700 800 900 1000 1100 qe [%] wavelength [nm] mono red green1 green2 blue figure 4. quantum efficiency curve for standard and nir mono qe [%] wavelength [nm] 0 10 20 30 40 50 60 300 400 500 600 700 800 900 1000 1100 mono nir
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 8 ray angle and microlens array information an array of microlenses is placed over the cmos pixel array in order to improve the absolute responsivity of the photodiodes. the combined microlens array and pixel array has two important properties: 1. angular dependency of photoresponse of a pixel the photoresponse of a pixel with microlens in the center of the array to a fixed optical power with varied incidence angle is as plotted in figure 5, where definitions of angles x and y are as described by figure 6. 2. microlens shift across array and cra the microlens array is fabricated with a slightly smaller pitch than the array of photodiodes. this difference in pitch creates a varying degree of shift of a pixel?s microlens with regards to its photodiode. a shift in microlens position versus photodiode position will cause a tilted angle of peak photoresponse, here denoted chief ray angle (cra). microlenses and photodiodes are aligned with 0 shift and cra in the center of the array, while the shift and cra increases radially towards its edges, as illustrated by figure 7.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 9 the purpose of the shifted microlenses is to improve the uniformity of photoresponse when camera lenses with a finite exit pupil distance are used. in the standard version of pythonxk, the cra varies nearly linearly with distance from the center as illustrated in figure 8, with a corner cra of approximately 10.6 degrees (for 5120 x 5120 resolution). this edge cra is matching a lens with exit pupil distance of 85 mm. figure 5. center pixel photoresponse to a fixed optical power with incidence angle varied along x and y 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?30 ?20 ?10 0 10 20 30 normalized response incidence angle x , y [degrees deviation from normal] x = 0 y = 0 note that the photoresponse peaks near normal incidence for center pixels. figure 6. definition of angles used in figure 5.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 10 figure 7. principle of microlens shift shift center pixel (aligned) edge pixel (with shift) the center axes of the microlens and the photodiode coincide for the center pixels. for the edge pixels, there is a shift between the axis of the microlens and the photodiode causing a peak response incidence angle (cra) that deviates from the normal of the pixel array. figure 8. variation of peak responsivity angle (cra) as a function of distance from the center of the array 0 2 4 6 8 10 12 0 5 10 15 20 diagonal x direction y direction cra [degrees] 7.5 10.6 distance from center [mm]
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 11 overview figure 9 gives an overview of the major functional blocks of the python sensor. figure 9. block diagram analog front end (afe) data formatting serializers & lvds interface lvds clock receiver control & registers biasing & bandgap 64 analog channels 64 x 10 bit digital channels 32 x 10 bit digital channels external resistor column structure image core bias image core row decoder reset spi interface pixel array 32, 16, 8, 4 multiplexed lvds output channels 1 lvds channel 1 lvds clock channel image core the image core consists of: ? pixel array ? address decoders and row drivers ? pixel biasing the python 25mp pixel array contains 5120 (h) x 5120 (v) readable pixels with a pixel pitch of 4.5 m. the python 16mp/12mp/10mp image arrays contain 4224 (h) x 4112 (v) / 4224 (h) x 3088 (v) / 3968 (h) x 2912 (v) readable pixels, inclusive of 8 pixel rows and 64 pixel columns at every side to allow for reprocessing or color reconstruction. the sensor uses in-pixel cds architecture, which makes it possible to achieve a low noise read out of the pixel array in both global shutter shutter mode with cds. the function of the row drivers is to access the image array to reset or read the pixel data. the row drivers are controlled by the on-chip sequencer and can access the pixel array. the pixel biasing block guarantees that the data on a pixel is transferred properly to the column multiplexer when the row drivers select a pixel line for readout. lvds clock receiver the lvds clock receiver receives an lvds clock signal and distributes the required clocks to the sensor. typical input clock frequency is 360 mhz. the clock input needs to be terminated with a 100 resistor. column multiplexer the 5120 pixels of one image row are stored in 5120 column sample-and-hold (s/h) stages. these stages store both the reset and integrated signal levels. the data stored in the column s/h stages is read out through 64 parallel differential outputs operating at a frequency of 36 mhz.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 12 at this stage, the reset signal and integrated signal values are transferred into an fpn-corrected differential signal. a programmable gain of 1x, 2x, or 4x can be applied to the signal at this stage. the column multiplexer also supports a subsampled readout mode (read-1-skip-1 for mono and read-2-skip-2 for color version). enabling this mode can speed up the frame rate, with a decrease in resolution. bias generator the bias generator generates all required reference voltages and bias currents that the on-chip blocks use. an external resistor of 47 k , connected between the pins ibias_master and ibias_out is required for the bias generator to operate properly. analog front end the afe contains 64 channels, each containing a pga and a 10-bit adc. for each of the 64 channels, a pipelined 10-bit adc is used to convert the analog image data into a digital signal, which is delivered to the data formatting block. a black calibration loop is implemented to ensure that the black level is mapped to match the correct adc input level. data formatting the data block receives data from two adcs and multiplexes this data to one lvds block. a cyclic redundancy check (crc) code is calculated on the passing data. for each lvds output channel, one data block is instantiated. an extra data block is foreseen to transmit synchronization codes such as frame start, line start, frame end, and line end indications. the data block calculates a crc once per line for every channel. this crc code can be used for error detection at the receiving end. serializer and lvds interface the serializer and lvds interface block receives the formatted (10-bit) data from the data formatting block. this data is serialized and transmitted by the lvds output driver. the maximum output data bit rate is 720 mbps per channel. in addition to the 32 lvds data outputs, two extra lvds outputs are available. one of these outputs carries the output clock, which is skew aligned to the output data channels. the second lvds output contains frame format synchronization codes to serve system-level image reconstruction. sequencer the sequencer: ? controls the image core. starts and stops integration and controls pixel readout. ? operates the sensor in master or slave mode. ? applies the window settings. organizes readouts so that only the configured windows are read. ? controls the column multiplexer and analog core. applies gain settings and subsampling modes at the correct time, without corrupting image data. ? starts up the sensor correctly when leaving standby mode.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 13 operating modes global shutter mode the python operates in pipelined or triggered global shutter modes. in this mode, light integration takes place on all pixels in parallel, although subsequent readout is sequential. figure 10 shows the integration and readout sequence for the global shutter mode. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and readout can occur in parallel or sequentially. the integration starts at a certain period, relative to the frame start. pipelined global shutter mode in pipelined global shutter mode, the integration and readout are done in parallel. images are continuously read and integration of frame n is ongoing during readout of the previous frame n?1. the readout of every frame starts with a frame overhead time (fot), during which the analog value on the pixel diode is transferred to the pixel memory element. after the fot, the sensor is read out line by line and the readout of each line is preceded by the row overhead time (rot). figure 11 shows the exposure and readout time line in pipelined global shutter mode. figure 10. global shutter operation master mode in this operation mode, the integration time is set through the register interface and the sensor integrates and reads out the images autonomously. the sensor acquires images without any user interaction. slave mode the slave mode adds more manual control to the sensor. the integration time registers are ignored in this mode and the integration time is instead controlled by an external pin. as soon as the control pin is asserted, the pixel array goes out of reset and integration starts. the integration continues until the user or system deasserts the external pin. upon a falling edge of the trigger input, the image is sampled and the readout begins. figure 11. pipelined shutter operation in master mode reset n exposure time n reset n+1 exposure time n+1 readout frame n-1 fot fot readout frame n rot line readout fot fot figure 12. pipelined shutter operation in slave mode reset n exposure time n reset n+1 exposure t im e n+1 readout n?1 fot fot readout n
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 14 triggered global shutter in this mode, manual intervention is required to control both the integration time and the start of readout. after the integration time, indicated by a user controlled pin, the image core is read out. after this sequence, the sensor goes to an idle mode until a new user action is detected. the three main differences from the pipelined shutter master mode are: ? upon user action, a single image is read. ? normally, integration and readout are done sequentially. however, the user can control the sensor in such a way that two consecutive batches are overlapping, that is, having concurrent integration and readout. ? integration and readout is user-controlled through an external pin. this mode requires manual intervention for every frame. the pixel array is kept in reset state until requested. the triggered global mode can also be controlled in a master or in a slave mode. master mode in this mode, a rising edge on the synchronization pin is used to trigger the start of integration and readout. the integration time is defined by a register setting. the sensor autonomously integrates during this predefined time, after which the fot starts and the image array is readout sequentially. a falling edge on the synchronization pin does not have any impact on the readout or integration and subsequent frames are started again for each rising edge. figure 13 shows the relation between the external trigger signal and the exposure/readout timing. if a rising edge is applied on the external trigger before the exposure time and fot of the previous frame is complete, it is ignored by the sensor. slave mode integration time control is identical to the pipelined shutter slave mode. an external synchronization pin controls the start of integration. when it is de?asserted, the fot starts. the analog value on the pixel diode is transferred to the pixel memory element and the image readout can start. a request for a new frame is started when the synchronization pin is asserted again. figure 13. triggered shutter operation in master mode reset n exposure time n reset n+1 exposure time n+1 readout n-1 fot fot readout n rot line readout external trigger no effect on falling edge register controlled fot fot
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 15 non?zero and zero row overhead time (rot) modes in pipelined global shutter mode, the integration and readout are done in parallel. images are continuously read out and integration of frame n is ongoing during readout of the previous frame n?1. the readout of every frame starts with a frame overhead time (fot), during which the analog value of the pixel diode is transferred to the pixel memory element. after the fot, the sensor is read out line by line and the readout of each line is preceded by a row overhead time (rot) as shown in figure 14. in reduced/zero rot operation mode (refer to figure 15), the row blanking and kernel readout occur in parallel. this mode is called reduced rot as a part of the rot is done while the image row is readout. the actual rot can thus be longer, however the perceived rot will be shorter (?overhead? spent per line is reduced). this operation mode can be used for two reasons: ? reduced total line time. ? lower power due to reduced clock rate. figure 14. integration and rea dout sequence of the sensor operating in pipelined global shutter mode with non?zero rot readout. rot ys rot ys+1 rot ye readout ye valid data fot () readout ys readout ys figure 15. integration and rea dout sequence of the sensor operating in pipelined global shutter mode with zero rot readout. rot ys (blanked out ) rot readout ys+1 ys rot readout ye ye?1 rot readout dummy ye valid data fot ()
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 16 sensor operation flowchart figure 16 shows the flow chart diagram of the sensor operation. the sensor can be in five dif ferent ?states?. every state is indicated with an oval circle. these states are: ? power-off ? standby (1) ? standby (2) ? idle ? running the states above are ordered by power dissipation. clearly, in ?power-off? state the power dissipation will be minimal; in ?running? state the power dissipation will be maximal. on the other hand, the lower the power consumption, the more actions (and time) are required to put the sensor in ?running? state and grab images. this flowchart provides the trade-offs between power saving and enabling time of the sensor. next to the ?states? a set of ?user actions?, indicated by arrows, are included in the flow chart diagram. these user actions make it possible to move from one state to another. figure 16. sensor operation flowchart
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 17 sensor states the sensor can be in five different states: power-off in this state, the sensor is inactive. all power supplies are down and the power dissipation is zero. standby (1) the registers below address 40 can be configured. standby (2) in this standby state all spi registers are active, meaning that all spi registers can be accessed for read and write operations. all other blocks are disabled. note: an intermediate standby state is traversed after a hard reset. in this state the sensor contains the default configurations. uploads of reserved registers are required to traverse to the standby (2) state idle in the idle state, all sensor clocks are running and all blocks are enabled, except the sequencer block. the sensor is ready to start grabbing images as soon as the sequencer block is enabled. running in running state, the sensor is enabled and grabbing images. the sensor can be operated in different global master/slave modes. user actions: power up functional mode sequences power-up sequence figure 17 shows the power-up timing of the sensor. apply all power supplies in the order shown in the figure. it is important to comply with the described sequence. any other supply ramping sequence may lead to high current peaks and, as a consequence, a failure of the sensor power up. the clock input should start running when all supplies are stabilized. note that before starting the clock, the lvds output channel multiplexing (32, 16, 8 or 4), by connecting pins f24/f25 (muxmode0/1), should be set to the correct supply as described in table 31 and table 28. when the clock frequency is stable, the reset_n signal can be de?asserted. after a wait period of 10 s, the power up sequence is finished and the first spi upload can be initiated. figure 17. power?up procedure reset_n vddd_18 vddd_33 vdda_33 lvds clock other supplies vdd_casc > 10us > 10us > 10us > 10us > 10us > 10us note: vdd_casc should come up prior to vdd_resfd, vdd_trans, vdd_calib and vdd_sel. enable clock management the ?enable clock management? action configures the clock management blocks in a pre?defined way. the required uploads are listed in table 6. table 6. enable clock management register upload upload # address data description 1 2 0x0000 monochrome 0x0001 color 2 34 0x0001 enable logic blocks
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 18 required register uploads in this phase the ?reserved? register settings are uploaded through the spi register. different settings are not allowed and may cause the sensor to malfunction. the required uploads are listed in table 7. table 7. required register uploads for, non?zero rot, pipelined global shutter master mode upload # address data (non?zero rot) 1 41 0x0b5a 2 42 0x1001 3 43 0x018d 4 65 0x88cb 5 66 0x53c7 6 67 0x8567 7 69 0x0488 8 70 0x48ff 9 128 0x360a 10 129 0x0001 11 192 0x000c 12 193* 0x8600 13 194 0x0224 14 197 0x0103 15 204 0x01e4 16 211 0x0e59 17 215 0x0007 18 216 0x7f00 19 219 0x0015 20 220 0x192c 21 224 0x3e07 22 225 0x5ef1 23 227 0x0000 24 237 0xc0a0 25 238 0x8f88 26 384 0xe800 27 385 0xf801 28 386 0xfb1f 29 387 0xfb15 30 388 0xf911 31 389 0xf901 32 390 0xf105 33 391 0xf30f 34 392 0xf201 35 393 0xe001 36 394 0xe021 upload # address data (non?zero rot) 37 395 0xe061 38 396 0xe265 39 397 0xe061 40 398 0xe041 41 399 0xe001 42 400 0xe406 43 401 0xe005 44 402 0xe20a 45 403 0xe001 46 404 0xe800 47 405 0xe800 48 406 0xec0a 49 407 0xe80a 50 408 0xe800 51 409 0x0030 52 410 0x217b 53 411 0x2071 54 412 0x0071 55 413 0x107f 56 414 0x107f 57 415 0x107f 58 416 0x1075 59 417 0x0071 60 418 0x0036 61 419 0x21bb 62 420 0x20b1 63 421 0x00b1 64 422 0x10bf 65 423 0x10bf 66 424 0x10bf 67 425 0x10b5 68 426 0x00b1 69 427 0x0030 70 428 0x0030 71 429 0x207b 72 430 0x2071 73 431 0x0071 74 432 0x107f 75 433 0x107f 76 434 0x107f 77 435 0x1075 78 436 0x0071
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 19 upload # address data (non?zero rot) 79 437 0x0036 80 438 0x21bb 81 439 0x20b1 82 440 0x00b1 83 441 0x10bf 84 442 0x10bf 85 443 0x10bf 86 444 0x10b5 87 445 0x00b1 88 446 0x0030 upload # address data (zero rot) 12 193* 0x0800 note: required uploads for zero rot mode are the same as for non?zero rot mode with the exceptions noted. soft power up during the soft power-up action, the internal blocks are enabled and prepared to start processing the image data stream. this action exists of a set of spi uploads. the soft power-up uploads are listed in table 8. table 8. soft power up register uploads upload # address data description p1?sn/se 1 32 0x2005 enable analogue clock 2 64 0x0001 enable biasing block 3 40 0x0003 enable column multiplexer 4 48 0x0001 enable analog front-end (afe) 5 68 0x0088 enable lvds bias 6 112 0x0007 enable lvds transmitters enable sequencer during the ?enable sequencer?-action, the frame grabbing sequencer is enabled. the sensor will start grabbing images in the configured operation mode. refer to operating modes on page 13 for an overview of the possible operation modes. the ?enable sequencer ? action consists of a set op register uploads. the required uploads are listed in table 9. table 9. enable sequencer register uploads upload # address data 1 192 0x000d user actions: functional mode to power down sequences disable sequencer during the ?disable sequencer?-action, the frame grabbing sequencer is stopped. the sensor will stop grabbing images and returns to the idle mode. the ?disable sequencer? action consists of a set op register uploads. the required uploads are listed in table 10. table 10. disable sequencer register uploads upload # address data 1 192 0x000c soft power down during the soft power -down action, the internal blocks are disabled and the sensor is put in standby state in order to reduce the current dissipation. this action exists of a set of register uploads. the soft power-down uploads are listed in table 11. table 11. soft power down register uploads upload # address data description p1?sn/se 1 112 0x0000 disable lvds transmitters 2 48 0x0000 disable analog front-end (afe) 3 40 0x0000 disable column multiplexer 4 64 0x0000 disable biasing block 5 32 0x2004 disable analogue clock
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 20 disable clock management the ?disable clock management?-action stops the internal clocking in order to further decrease the power dissipation. this action exists of a set of register uploads as listed in table 12. table 12. disable sequencer register uploads no. address data description 1 34 0x0000 disable logic blocks power-down sequence the timing diagram of the advised power -down sequence is given in figure 18. any other sequence might cause high peak currents. note: vdd_casc should be powered down after vdd_resfd, vdd_trans, vdd_calib and vdd_sel. figure 18. power?down sequence reset_n vddd_18 vddd_33 vdda_33 lvds clock other supplies vdd_casc > 10u s > 10 us > 10us > 1 0us > 10us > 10us table 13. shutter/operation mode configuration registers address default value description 192 [4] 0x0 triggered mode selection 0: normal mode 1: triggered mode 192 [5] 0x0 master/slave selection 0: master mode 1: slave mode 192 [7] 0x0 subsampling mode selection 0: subsampling disabled 1: subsampling enabled 192 [8] 0x0 binning mode selection 0: binning disabled 1: binning enabled windowing reconfiguration the windowing settings can be configured during standby, idle, and running mode. the required regions of interest (roi) can be programmed in the roi_configuration registers (addresses 256 up to 351). registers roi_active0 and roi_active1 are used to activate the desired rois. default window configuration (after sensor reset) is one window, full frame (window #0). exposure/gain reconfiguration the exposure time and gain settings can be configured during standby, idle, and running mode. refer to signal gain path on page 32 for more information.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 21 sensor configuration this device contains multiple configuration registers. some of these registers can only be configured while the sensor is not acquiring images (while register 192[0] = 0), while others can be configured while the sensor is acquiring images. for the latter category of registers, it is possible to distinguish the register set that can cause corrupted images (limited number of images containing visible artifacts) from the set of registers that are not causing corrupted images. these three categories are described here. static readout parameters some registers are only modified when the sensor is not acquiring images. reconfiguration of these registers while images are acquired can cause corrupted frames or even interrupt the image acquisition. therefore, it is recommended to modify these static configurations while the sequencer is disabled (register 192[0] = 0). the registers are shown in table 14. t able 14 should not be reconfigured during image acquisition. a specific configuration sequence applies for these registers. refer to the operation flow and startup description. table 14. static readout parameters group addresses description clock generator 32 configure according to recommendation image core 40 configure according to recommendation afe 48 configure according to recommendation bias 64?71 configure according to recommendation lvds 112 configure according to recommendation sequencer mode selection 192 ? triggered_mode ? slave_mode all reserved registers keep reserved registers to their default state, unless otherwise described in the recommendation dynamic configuration potentially causing image artifacts the category of registers as shown in table 15 consists of configurations that do not interrupt the image acquisition process, but may lead to one or more corrupted images during and after the reconfiguration. a corrupted image is an image containing visible artifacts. a typical example of a corrupted image is an image which is not uniformly exposed the effect is transient in nature and the new configuration is applied after the transient effect. table 15. dynamic configuration potentially causing image artifacts group addresses description black level configuration 128?129 197[12:8] reconfiguration of these registers may have an impact on the black-level calibration algorithm. the effect is a transient number of images with incorrect black level compensation. sync codes 129[13] 116?126 incorrect sync codes may be generated during the frame in which these registers are modified. datablock test configurations 144?150 modification of these registers may generate incorrect test patterns during a transient frame. dynamic readout parameters it is possible to reconfigure the sensor while it is acquiring images. frame-related parameters are internally resynchronized to frame boundaries, such that the modified parameter does not affect a frame that has already started. however, there can be restrictions to some registers as shown in table 16. some reconfiguration may lead to one frame being blanked. this happens when the modification requires more than one frame to settle. the image is blanked out and training patterns are transmitted on the data and sync channels.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 22 table 16. dynamic readout parameters group addresses description subsampling/binning 192[7] 192[8] subsampling or binning is synchronized to a new frame start. roi configuration 195-196 256?351 an roi switch is only detected when a new window is selected as the active window (reconfiguration of registers 195, 196, or both). reconfiguration of the roi dimension of the active window does not lead to a frame blank and can cause a corrupted image. exposure reconfiguration 199-201 exposure reconfiguration does not cause artifact. however, a latency of one frame is observed unless reg_seq_exposure_sync_mode is set to ?1? in triggered global mode (master). gain reconfiguration 204 gains are synchronized at the start of a new frame. optionally, one frame latency can be incorporated to align the gain updates to the exposure updates (refer to register 204[13] gain_lat_comp). freezing active configurations though the readout parameters are synchronized to frame boundaries, an update of multiple registers can still lead to a transient effect in the subsequent images, as some configurations require multiple register uploads. for example, to reconfigure the exposure time in master global mode, both the fr_length and exposure registers need to be updated. internally, the sensor synchronizes these configurations to frame boundaries, but it is still possible that the reconfiguration of multiple registers spans over two or even more frames. to avoid inconsistent combinations, freeze the active settings while altering the spi registers by disabling synchronization for the corresponding functionality before reconfiguration. when all registers are uploaded, re-enable the synchronization. the sensor?s sequencer then updates its active set of registers and uses them for the coming frames. the freezing of the active set of registers can be programmed in the sync_configuration registers, which can be found at the spi address 206. figure 19 shows a reconfiguration that does not use the sync_configuration option. as depicted, new spi configurations are synchronized to frame boundaries. when sync_configuration = ?1?, configurations are synchronized to the frame boundaries (the registers exposure, fr_length, and mult_timer are not used in this mode) figure 20 shows the usage of the sync_configuration settings. before uploading a set of registers, the corresponding sync_configuration is deasserted. after the upload is completed, the sync_configuration is asserted again and the sensor resynchronizes its set of registers to the coming frame boundaries. as seen in the figure, this ensures that the uploads performed at the end of frame n+2 and the start of frame n+3 become active in the same frame (frame n+4). figure 19. frame synchronization of configurations (no freezing) frame nframe n+1?frame n+2?frame n+3 frame n+4 time line spi registers active registers figure 20. reconfiguration using sync_configuration frame nframe n+1?frame n+2?frame n+3?frame n+4 time line sync_configuration spi registers active registers this configuration is not taken into account as sync_register is inactive. note: spi updates are not taken into account while sync_configuration is inactive. the active configuration is frozen for the sensor. table 17 lists the several sync_configuration possibilities along with the respective registers being frozen.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 23 table 17. alternate sync configurations group affected registers description sync_black_lines black_lines update of black line configuration is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_exposure mult_timer fr_length exposure update of exposure configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_gain mux_gainsw afe_gain update of gain configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_roi roi_active0[15:0] roi_active1[15:0] subsampling binning update of active roi configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. note: the window configurations themselves are not frozen. re-configuration of active windows is not gated by this setting. window configuration global shutter mode up to 32 windows can be defined in global shutter mode (pipelined or triggered). the windows are defined by registers 256 to 351. each window can be activated or deactivated separately using registers 195 and 196. it is possible to reconfigure the inactive windows while acquiring images. switching between predefined windows is achieved by activation of the respective windows. this way a minimum number of registers need to be uploaded when it is necessary to switch between two or more sets of windows. as an example of this, scanning the scene at higher frame rates using multiple windows and switching to full frame capture when the object is tracked. switching between the two modes only requires an upload of one (if the total number of windows is smaller than 17) or two (if more than 16 windows are defined) registers. black calibration the sensor automatically calibrates the black level for each frame. therefore, the device generates a configurable number of electrical black lines at the start of each frame. the desired black level in the resulting output interface can be configured and is not necessarily targeted to ?0?. configuring the target to a higher level yields some information on the left side of the black level distribution, while the other end of the distribution tail is clipped to ?0? when setting the black level target to ?0?. the black level is calibrated for the 64 columns contained in one kernel. this implies 64 black level offsets are generated and applied to the corresponding columns. configurable parameters for the black-level algorithm are listed in table 18.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 24 table 18. configurable parameters for black level algorithm group addresses description black line generation 197[7:0] black_lines this register configures the number of black lines that are generated at the start of a frame. at least one black line must be generated. the maximum number is 255. note: when the automatic black-level calibration algorithm is enabled, make sure that this register is configured properly to produce sufficient black pixels for the black-level filtering. the number of black pixels generated per line is dependent on the operation mode and window configurations: each black line contains 80 kernels. 197[12:8] gate_first_line a number of black lines are blanked out when a value different from 0 is configured. these blanked out lines are not used for black calibration. it is recommended to enable this functionality, because the first line can have a different behavior caused by boundary effects. when enabling, the number of black lines must be set to at least two in order to have valid black samples for the calibration algorithm. black value filtering 129[0] auto_blackcal_enable internal black-level calibration functionality is enabled when set to ?1?. required black level offset compensation is calculated on the black samples and applied to all image pixels. when set to ?0?, the automatic black-level calibration functionality is disabled. it is possible to apply an offset compensation to the image pixels, which is defined by the registers 129[10:1]. note: black sample pixels are not compensated; the raw data is sent out to provide ex- ternal statistics and, optionally, calibrations. 129[9:1] blackcal_offset black calibration offset that is added or subtracted to each regular pixel value when au- to_blackcal_enable is set to ?0?. the sign of the offset is determined by register 129[10] (blackcal_offset_dec). note: all channels use the same offset compensation when automatic black calibration is disabled. the calculated black calibration factors are frozen when this register is set to 0x1ff (all??1?) in auto calibration mode. any value different from 0x1ff re?enables the black calibration algorithm. this freezing option can be used to prevent eventual frame to frame jitter on the black level as the correction factors are recalculated every frame. it is recom- mended to enable the black calibration regularly to compensate for temperature changes. 129[10] blackcal_offset_dec sign of blackcal_offset. if set to ?0?, the black calibration offset is added to each pixel. if set to ?1?, the black calibration offset is subtracted from each pixel. this register is not used when auto_blackcal_enable is set to ?1?. 128[10:8] black_samples the black samples are low-pass filtered before being used for black level calculation. the more samples are taken into account, the more accurate the calibration, but more samples require more black lines, which in turn affects the frame rate. the effective number of samples taken into account for filtering is 2 black_samples . note: an error is reported by the device if more samples than available are requested (refer to registers 136 to 139). black level filtering monitoring 136 137 138 139 blackcal_error0 blackcal_error1 blackcal_error2 blackcal_error3 an error is reported by the device if there are requests for more samples than are available (each bit corresponding to one data path). the black level is not compensated correctly if one of the channels indicates an error. there are three possible methods to overcome this situation and to perform a correct offset compensation: ? increase the number of black lines such that enough samples are generated at the cost of increasing frame time (refer to register 197). ? relax the black calibration filtering at the cost of less accurate black level determina- tion (refer to register 128). ? disable automatic black level calibration and provide the offset via spi register upload. note that the black level can drift in function of the temperature. it is thus recommended to perform the offset calibration periodically to avoid this drift. note: the maximum number of samples taken into account for black level statistics is half the number of kernels.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 25 serial peripheral interface the sensor configuration registers are accessed through an spi. the spi consists of four wires: ? sck: serial clock ? ss_n: active low slave select ? mosi: master out, slave in, or serial data in ? miso: master in, slave out, or serial data out the spi is synchronous to the clock provided by the master (sck) and asynchronous to the sensor?s system clock. when the master wants to write or read a sensor?s register, it selects the chip by pulling down the slave select line (ss_n). when selected, data is sent serially and synchronous to the spi clock (sck). figure 21 shows the communication protocol for read and write accesses of the spi registers. the python xk sensor uses 9-bit addresses and 16-bit data words data driven by the system is colored blue in figure 21, while data driven by the sensor is colored yellow. the data in grey indicates high-z periods on the miso interface. red markers indicate sampling points for the sensor (mosi sampling); green markers indicate sampling points for the system (miso sampling during read operations). the access sequence is: 3. select the sensor for read or write by pulling down the ss_n line. 4. one spi clock cycle (100 ns) after selecting the sensor, the 9-bit address is transferred, most significant bit first. the sck clock is passed through to the sensor as indicated in figure 21. the sensor samples this data on a rising edge of the sck clock (mosi needs to be driven by the system on the falling edge of the sck clock) 5. the tenth bit sent by the master indicates the type of transfer: high for a write command, low for a read command. 6. data transmission: - for write commands, the master continues sending the 16-bit data, most significant bit first. - for read commands, the sensor returns the requested address on the miso pin, most significant bit first. the miso pin must be sampled by the system on the falling edge of sck (assuming nominal system clock frequency and maximum 10 mhz spi frequency). 7. when data transmission is complete, the system deselects the sensor one clock period after the last bit transmission by pulling ss_n high. note the maximum frequency for the spi interface needs to scale with the lvds input clock frequency as described in table 5. consecutive spi commands can be issued by leaving at least two spi clock periods between two register uploads. deselect the chip between the spi uploads by pulling the ss_n pin high. figure 21. spi read and write timing diagram .. a1 a0 `1' a8 d15 d14 .. .. .. .. d1 d0 sck mo si ss_n sp i ? w r ite miso a7 .. .. .. a1 a0 `0' a8 sck mo si ss_n spi ? rea d miso a7 .. .. d15 d14 .. .. .. .. d1 d0 ts_mosi th_mosi t_sssck t_sc ks s ts _mi so th_mi so t_sc ks s t_sssck ts _mos i th_mosi ts ck ts ck
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 26 table 19. spi timing requirements group addresses description units tsck sck clock period 100 (*) ns tsssck ss_n low to sck rising edge tsck ns tsckss sck falling edge to ss_n high tsck ns ts_mosi required setup time for mosi 20 ns th_mosi required hold time for mosi 20 ns ts_miso setup time for miso tsck/2-10 ns th_miso hold time for miso tsck/2-20 ns tspi minimal time between two consecutive spi accesses (not shown in figure) 2 x tsck ns *value indicated is for nominal operation. the maximum spi clock frequency depends on the sensor configuration (operation mode, input clock). tsck is defined as 1/f spi . see text for more information on spi clock frequency restrictions.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 27 image sensor timing and readout global shutter mode pipelined global mode (master) the sensor timing in master global shutter mode is controlled by the user by means of configuration registers. one can distinguish three parameters for the frame timing in global shutter mode: ? image array reset length ? integration time ? frame length the relation between these parameters is: frame length = reset length + integration time the fot time needs to be added to the frame length parameter to determine the total frame time total frame time = fot time + frame length frame and integration time configuration can be controlled in two ways: 1. fr_mode = 0x0 the reset length and integration time is configured by the user. the sensor shall calculate the frame length as the sum of both parameters. 2. fr_mode = 0x1 the frame length and integration time is configured by the user. the reset time during which the pixels are reset, is calculated by the sensor as being the difference between the frame length and the desired integration time. the configuration registers are exposure[15:0] and fr_length[15:0]. the latter configuration register is either used as reset length configuration (fr_mode = 0x0) or as frame length (fr_mode = 0x1). the granularity of both registers is defined by the mult_timer[15:0] register and is expressed in number of 72 mhz cycles (13.889 ns nominal). reset length and integration time as parameters the reset time for the pixel array is controlled by the registers fr_length[15:0] and exposure[15:0]. the mult_timer configuration defines the granularity of the registers fr_length and exposure and is to be read as the number of 72 mhz cycles (13.889 ns nominal). the exposure control for pipelined global master mode is depicted in figure 22. the pixel values are transferred to the storage node during the fot, after which all photo diodes are reset. the reset state remains active for a certain time, defined by the fr_length and mult_timer registers, as shown in the figure. meanwhile, the image array is read out line by line. after this reset period, the global photodiode reset condition is abandoned. this indicates the start of the integration or exposure time. the length of the exposure time is defined by the registers exposure and mult_timer. notes: ? the start of the exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. therefore, the effective time during which the image core is in a reset state is extended to the start of a new line. ? make sure that the sum of the reset time and exposure time exceeds the time required to read out all lines. if this is not the case, the exposure time is extended until all (active) lines are read out. frame length and integration time as parameters when fr_mode is configured to 0x1, one configures the frame time and exposure. the reset_length is determined by the sequencer. this configuration mode is depicted in figure 2. the frame length is configured in register fr_length, while the integration time is configured in register exposure. the mult_timer register defines granularity of both settings. note that the fot needs to be added to the configured fr_length to calculate the total frame time. triggered global shutter (master) in master triggered global mode, the start of integration time is controlled by a rising edge on the trigger pin. the exposure or integration time is defined by the registers exposure and mult_timer, similar to the master pipelined global mode. the fr_length configuration is not used. this operation is graphically shown in figure 24. notes: ? the falling edge on the trigger pin does not have any impact. however, the trigger must be asserted for at least 100 ns. ? the start of the exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. therefore, the effective time during which the image core is in reset state is extended to the start of a new line. ? the trigger pin needs to be kept low during the fot. the monitor pins can be used as a feedback to the fpga/controller (eg. use monitor0, indicating the very first line when monitor_select = 0x5 ? a new trigger can be initiated after a rising edge on monitor0). if the exposure timer expires before the end of readout, the exposure time is extended until the end of the last active line.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 28 figure 22. integration control for pipelined global shutter mode (master, fr_mode = 0x0) reset integrating reset integrating image array global reset readout fot fot fot fot fot fot fr_length exposure frame n frame n+1 exposure state = rot = readout figure 23. integration control for pipelined global shutter mode (master, fr_mode = 0x1) reset integrating reset integrating image array global reset readout fot fot fot fot fot fot fr_length x mult_timer exposure x mult_timer frame n frame n+1 exposure state = rot = readout figure 24. exposure time control in triggered global mode (master) reset integrating reset integrating image array global reset readout fot fot fot fot fot fot exposure x mult_timer frame n frame n+1 exposure state (no effect on falling edge ) trigger0 = rot = readout triggered global shutter (slave) exposure or integration time is fully controlled by means of the trigger pin in slave mode. the registers fr_length, exposure, and mult_timer are ignored by the sensor. a rising edge on the trigger pin indicates the start of the exposure time, while a falling edge initiates the transfer and readout of the image array. in other words, the high time of the trigger pin indicates the integration time, the period of the trigger pin indicates the frame time. the use of the trigger during slave mode is shown in figure 25. notes: ? the start of the exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. therefore, the effective time during which the image core is in a reset state is extended to the start of a new line. ? if the trigger is deasserted before the end of readout, the exposure time is extended until the end of the last active line. consequently the fot and start of frame readout is postponed accordingly. ? the trigger pin needs to be kept low during the fot. the monitor pins can be used as a feedback to the fpga/controller (eg. use monitor0, indicating the very first line when monitor_select = 0x5 ? a new trigger can be initiated after a rising edge on monitor0).
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 29 figure 25. exposure time control in global?slave mode reset integrating reset integrating image array global reset readout fot fot fot fot fot fot frame n frame n+1 exposure state trigger = rot = readout
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 30 additional features multiple window readout the python sensor supports multiple window readout, which means that only the user?selected regions of interest (roi) are read out. this allows limiting data output for every frame, which in turn allows increasing the frame rate. in global shutter mode, up to 32 rois can be configured. window configuration figure 26 shows the four parameters defining a region of interest (roi). figure 26. region of interest configuration y-start y-end x-start?x-end roi 0 ? x?start[6:0] x?start defines the x?starting point of the desired window. the sensor reads out 64 pixels in one single clock cycle. as a consequence, the granularity for configuring the x?start position is also 64 pixels. the value configured in the x?start register is multiplied by 64 to find the corresponding column in the pixel array. ? x?end[6:0] this register defines the window end point on the x?axis. similar to x?start, the granularity for this configuration is one kernel. x?end needs to be larger than x?start. ? y?start[9:0] the starting line of the readout window. the granularity of this setting is one line, except with color sensors where it needs to be an even number. ? y?end[9:0] the end line of the readout window. y?end must be configured larger than y?start. this setting has the same granularity as the y?start configuration. up to thirty?two windows can be defined, possibly (partially) overlapping, as illustrated in figure 27. figure 27. overlapping multiple window configuration y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi 0 roi 1 the sequencer analyses each line that need to be read out for multiple windows. restrictions the following restrictions for each line are assumed for the user configuration: ? windows are ordered from left to right, based on their x?start address: x_start_roi(i) x_start_roi(j) and x_end_roi(i) x_end_roi(j) where j i > processing multiple windows the sequencer control block houses two sets of counters to construct the image frame. as previously described, the y?counter indicates the line that needs to be read out and is incremented at the end of each line. for the start of the frame, it is initialized to the y?start address of the first window and it runs until the y?end address of the last window to be read out. the last window is configured by the configuration registers and it is not necessarily window #31. the x?counter starts counting from the x?start address of the window with the lowest id which is active on the addressed line. only windows for which the current y?address is enclosed are taken into account for scanning. other windows are skipped. figure 28 illustrates a practical example of a configuration with five windows. the current position of the
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 31 read pointer (ys) is indicated by a red line crossing the image array. for this position of the read pointer, three windows need to be read out. the initial start position for the x?kernel pointer is the x?start configuration of roi1. kernels are scanned up to the roi3 x?end position. from there, the x?pointer jumps to the next window, which is roi4 in this illustration. when reaching roi4?s x?end position, the read pointer is incremented to the next line and xs is reinitialized to the starting position of roi1. notes: ? the starting point for the readout pointer at the start of a frame is the y?start position of the first active window. ? the read pointer is not necessarily incremented by one, but depending on the configuration, it can jump in y?direction. in figure 28, this is the case when reaching the end of roi0 where the read pointer jumps to the y?start position of roi1 ? the x?pointer starting position is equal to the x?start configuration of the first active window on the current line addressed. this window is not necessarily window #0. ? the x?pointer is not necessarily incremented by one each cycle. at the end of a window it can jump to the start of the next window. ? each window can be activated separately. there is no restriction on which window and how many of the 8 windows are active. figure 28. scanning the image array with five windows roi 0 roi 1 roi 4 ys roi 3 roi 2 subsampling and binning pixel binning and subsampling methods are used as a way of decimating the image. the number of pixel samples is reduced by a factor of four, while the optical area is maintained. pixel binning pixel binning is a technique in which different pixels belonging to a rectangular bin are averaged in the analog domain. two-by-two pixel binning is implemented in the python xk sensor . this implies that two adjacent pixels are averaged both in column and row. binning is configurable using a register setting. pixel binning is not supported on python xk color option. notes: 1. binning can be activated for the x and y direction independently by means of the binning_mode register. refer to the registermap for more information. 2. binning in the y?direction is not supported in conjunction with zero rot mode. subsampling subsampling is obtained by adapting the readout sequence. in subsampling mode, both lines and pixels are read in a read-n-skip-n mode. this reduces the number of lines in a frame and the number of pixels in a line. overall frame time is reduced by a factor 4. subsampling can be configured for the x and y direction independently by means of the subsampling_mode register. the monochrome sensor is read out in a read-one-skip-one pattern for both the rows and the columns, while the color version supports a read-two-skip-two subsampling scheme. this mode is selectable through register configuration. figure 29 shows which pixels are read and which ones are skipped for monochrome and color sensors respectively. readout direction is indicated as an x and y arrow.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 32 figure 29. subsampling scheme for python xk signal gain path table 20 and t able 21 show the available registers (fields) to program the desired exposure time and gain settings. table 20. exposure time configuration registers address default value description 201 0x0000 exposure time: granularity defined by ?mult timer? (register 199). 199 0x0001 mult timer defines granularity of exposure and reset length. unit = 1/72 mhz for normal rot mode 200 0x0000 reset length or frame length granularity defined by ?mult timer? (register 199) table 21. gain configuration registers address unity gain config- uration description 204 [4:0] 0x04 0x04: 1x 0x18: 1.26x 0x08: 1.87x 0x10: 3.17x 204 [13] postpone gain update by one frame when ?1? to compensate for exposure time updates latency. 205[11:0] 0x080 digital gain, 5.7 unsigned representation (5 bits before decimal point, 7 bits after fractional part). maximum gain is 31.992
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 33 mode changes and frame blanking dynamically reconfiguring the sensor may lead to corrupted or non-uniformilly exposed frames. for some reconfigurations, the sensor automatically blanks out the image data during one frame. frame blanking is summarized in the following table for the sensor?s image related modes. note: major mode switching (i.e. switching between master, triggered or slave mode) must be performed while the sequencer is disabled (reg_seq_enable = 0x0). table 22. dynamic sensor reconfiguration and frame blanking configuration corrupted frame blanked out frame notes shutter mode and operation triggered_mode do not reconfigure while the sensor is acquiring images. disable image acquisition by setting reg_seq_enable = 0x0. slave_mode do not reconfigure while the sensor is acquiring images. disable image acquisition by setting reg_seq_enable = 0x0. subsampling enabling: no disabling: yes configurable configurable with blank_subsampling_ss register. binning no configurable configurable with blank_subsampling_ss register frame timing black_lines no no exposure control mult_timer no no latency is 1 frame fr_length no no latency is 1 frame exposure no no latency is 1 frame gain mux_gainsw no no latency configurable by means of gain_lat_comp register afe_gain no no latency configurable by means of gain_lat_comp register. db_gain no no latency configurable by means of gain_lat_comp register. window/roi roi_active see note no windows containing lines previously not read out may lead to corrupted frames. roi*_configuration* see note no reconfiguring the windows by means of roi*_configuration* may lead to corrupted frames when configured close to frame boundaries. it is recommended to (re)configure an inactive window and switch the roi_active register. see notes on roi_active. black calibration black_samples no no if configured within range of configured black lines auto_blackal_enable see note no manual correction factors become instantly active when auto_blackcal_enable is deasserted during operation. blackcal_offset see note no manual blackcal_offset updates are instantly active. crc calculation crc_seed no no impacts the transmitted crc sync channel bl_0 no no impacts the sync channel information, not the data channels. img_0 no no impacts the sync channel information, not the data channels. crc_0 no no impacts the sync channel information, not the data channels. tr_0 no no impacts the sync channel information, not the data channels.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 34 sensor status the currently used exposure and gain parameters are reported by the sensor in registers 240 to 248. these status registers are updated at the start of the frame in which these parameters become active. temperature diode the temperature diode allows the monitoring of the sensor die temperature during operation. the diode can be connected through the pins td_anode and td_cathode. the die temperature (tdie), as a function of the measured forward threshold voltage of the diode, with a known bias current (vdiode at bias 40 a), is determined according to the following formula: t die = (0.77?vdiode at bias 40 a)/0.00158 c temperature sensor the python has an on?chip temperature sensor which returns a digital code (tsensor) of the silicon junction temperature. the tsensor output is a 8?bit digital count between 0 and 255, proportional to the temperature of the silicon substrate. this reading can be translated directly to a temperature reading in c by calibrating the 8?bit readout at 0 c and 85 c to achieve an output accuracy of 2 c. the tsensor output can also be calibrated using a single temperature point (example: room temperature or the ambient temperature of the application), to achieve an output accuracy of 5 c. note that any process variation will result in an offset in the bit count and that offset will remain within 5 c over the temperature range of 0 c and 85 c. tsensor output digital code can be read out through the spi interface. output of the temperature sensor to the spi: tempd_reg_temp<7:0>: this is the 8?bit n count readout proportional to temperature. input from the spi: the reg_tempd_enable is a global enable and this enables or disables the temperature sensor when logic high or logic low respectively. the temperature sensor is reset or disabled when the input reg_tempd_enable is set to a digital low state. calibration using one temperature point the temperature sensor resolution is fixed for a given type of package for the operating range of 0 c to +85 c and hence devices can be calibrated at any ambient temperature of the application, with the device configured in the mode of operation. interpreting the actual temperature for the digital code readout: the formula used is t j = r (nread ? ncalib) + tcalib t j = junction die temperature r = resolution in degrees/lsb (typical 0.75 deg/lsb) nread = tsensor output (lsb count between 0 and 255) tcalib = tsensor calibration temperature ncalib = tsensor output reading at tcalib monitor pins the sensor features three logic monitor output pins. these pins can provide internal state and synchronization information to the outside system. these status pins can be used during system setup or for system frame synchronization. the pins are named monitor0, monitor1, and monitor2. the information provided on these pins is configured with the register monitor_select (register 192[13:11]). note: monitor indications are generated in the sequencer. these signals lead the image and synchronization data on the lvds channels.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 35 table 23. monitor select monitor select monitor output description 0x0 monitor0: ?0? no information is provided on the output pins. all outputs are driven to logic ?0? monitor1: ?0? monitor2: ?0? 0x1 monitor0: integration time indication high during integration monitor1: rot indication high when rot is active, low outside rot monitor2: dummy line indication high during dummy lines, low during all other lines 0x2 monitor0: integration time indication high during integration monitor1: n/a n/a monitor2: n/a n/a 0x3 monitor0: start of x-readout pulse indicating the start of x-readout monitor1: black line indication high during black lines, low during all other lines monitor2: dummy line indication high during dummy lines, low during all other lines 0x4 monitor0: frame start pulse indicating the start of a new frame monitor1: start of rot pulse indicating the start of rot monitor2: start of x-readout pulse indicating the start of x-readout 0x5 monitor0: first line indication high during the first line of each frame, low for all others monitor1: start of rot indication pulse indicating the start of rot monitor2: rot inactive low when rot is active, high outside rot 0x6 monitor0: rot indication high when rot is active, low outside rot monitor1: start of x-readout pulse indicating the start of x-readout monitor2: x-readout inactive low during x-readout, high outside x-readout 0x7 monitor0: start of x-readout for black lines pulse indicating the start of x-readout for black lines monitor1: start of x-readout for image lines pulse indicating the start of x-readout for image lines monitor2: start of x-readout for dummy lines pulse indicating the start of x-readout for dummy lines
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 36 data output format lvds output channels the image data output occurs through 32 lvds data channels, operating at 720 mbps. a synchronization lvds channel and an lvds output clock signal synchronizes the data. the 32 data channels are used to output the image data only. the sync channel transmits information about data sent over these data channels (includes codes indicating black pixels, normal pixels, and crc). to perform word synchronization on the output data stream, a predefined training pattern is sent after startup of the sensor and during idle times (during fot, rot, and in between frames and lines). this data is used to perform word alignment on the receiving side. the words on data and sync channels have a 10-bit length. the words are serialized most significant bit first. the output data rate is 720 mbps. serial link interface operation this sensor?s serial link interface is based on a mesochronous clocking system. this means that all data and control links operate at the same frequency, but their phase may be different due to skew. the host provides an lvds clock as input to the sensor. to compensate for possible large on-chip delays, the sensor retransmits this clock with the same delay as that seen by the data (32 data channels) and control path (one sync channel). the receiver end (generally an fpga-based system) performs per-interface skew compensation. the data on high-speed serial links can drift due to various reasons such as skew, jitter, pcb trace delays, process, voltage, and temperature variations. the receiver performs per-lvds interface skew compensation using bit and word alignment techniques. to support per-interface skew compensation, the sensor provides a training mode that allows the system to perform bit and word alignment on all interfaces. during idle moments (when the sensor is not capturing images or during frame and line overhead), the image sensor transmits training patterns. these patterns are configurable by means of a register upload and should be chosen such that these can easily be detected by reducing the risk of mimicking in the regular data stream. bit alignment bit alignment procedures position the sampling edge of the clock at the center of the data eye window by adding delay to the data path (using delay taps). word alignment word alignment procedures ensure that the reconstructed parallel data bits are in correct order at the output of the deserializer. word alignment is done by looking for well known training patterns. all major fpga vendors provide bit and word alignment methods for their fpgas. refer to the fpga vendor?s application for more information on the use of these functionalities. when the host succeeds in a lock for bit and word alignment procedures, the system enables the sensor for image acquisition. specific frame alignment patterns are transmitted for image frame synchronization purposes. frame format the frame format is explained by example of the readout of two (overlapping) windows, as shown in figure 30 (a). the readout of a frame occurs on a line-by-line basis. in this representation, the read pointer goes from left to right, bottom to top. figure 30 indicates that, after the fot is complete, a number of lines which only include information of ?roi 0? are sent out, starting at position y0_start. when the line at position y1_start is reached, a number of lines containing data of ?roi 0? and ?roi 1? are sent out, until the line position of y0_end is reached. from there on, only data of ?roi 1? appears on the data output channels until line position y1_end is reached. note: only frame start and frame end sync words are indicated in (b). crc codes are also omitted from figure 30. during readout of image data over the data channels, the sync channel sends out frame synchronization codes, which provide information related to the image data being sent over the 32 data output channels. each line of a window starts with a line start (ls) indication and ends with a line end (le) indication. the line start of the first line is replaced by a frame start; the line end of the last line is replaced with a frame end indication. each such frame synchronization code is followed by a window id (range 0 to 31). the data channels contain valid pixel data during fs/fe/ls/le and window id synchronization codes. note: for overlapping windows, the line synchronization codes of the overlapping windows with lower ids are not sent out. as shown in the illustration, no le is transmitted for the overlapping part of window 0. black lines are read out at the start of a frame. these lines are enclosed by ls and le indications (no frame start/end). the window id for the black lines must be ignored.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 37 figure 30. frame sync codes (a) (b) y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi 0 reset n exposure time n reset n+1 exposure time n+1 roi 0 fot fot integration time handling readout handling fot roi 1 readout frame n-1 readout frame n roi 0 roi 1 fs0 fs1 fe1 fs0 fs1 fe1 figure 31 and figure 32 show the details of the readout of a number of lines for single window readout, at the beginning of the frame. figure 33 shows the details of the readout of a number of lines for two overlapping windows. figure 31. timeline showing readout of black line for global shutter data channels sync channel data channels sync channel sequencer internal state line ys line ys+1 line ye black timeslot 0 training tr ls training tr fot rot rot rot rot crc bl timeslot 1 timeslot 77 timeslot 78 timeslot 79 crc timeslot bl 0 blblblblle 0
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 38 figure 32. timeline for single window readout data channels sync channel data channels sync channel sequencer internal state line ys line ys+1 line ye black timeslot xstart training tr fs id training tr id rot crc img timeslot xstart + 1 timeslot xend - 2 timeslot xend - 1 timeslot xend crc timeslot img le rot rot rot fot img img img img note: in the figure, the second image line is shown in more detail. the ls code is replaced by fs for the first line and the le code is replaced by fe for the last line in the window. figure 33. timeline showing readout of two overlapping windows data channels sync channel data channels sync channel sequencer internal state line ys+1 line ye black timeslot xstartm training tr ls idm img le training tr idn rot crc img timeslot xstartn timeslot xendn line ys img rot rot rot fot ls idn img img timeslot xstartm +1 timeslot xstartn -1 crc timeslot
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 39 frame synchronization table 24 sh ows the structure of the frame synchronization code. note that the table shows the default data word (configurable). if more than one window is active at the same time, the sync channel transmits the frame synchronization codes of the window with highest index only. table 24. frame synchronization code details sync word bit position register address default value description 9:7 n/a 0x5 frame start (fs) indication 9:7 n/a 0x6 frame end (fe) indication 9:7 n/a 0x1 line start (ls) indication 9:7 n/a 0x2 line end (le) indication 6:0 117[6:0] 0x2a these bits indicate that the received sync word is a frame synchronization code. the value is programmable by a register setting window identification frame synchronization codes are always followed by a 4?bit window identification (bits 3:0). this is an integer number, ranging from 0 to 15, indicating the active window. if more than one window is active for the current cycle, the highest window id is transmitted. data classification codes for the remaining cycles, the sync channel indicates the type of data sent through the data links: black pixel data (bl), image data (img), or training pattern (tr). these codes are programmable by a register setting. the default values are listed in table 25. table 25. synchronization channel default identification code values sync word bit position register address default value description 9:0 118 [9:0] 0x015 black pixel data (bl). this data is not part of the image. the black pixel data is used internally to correct channel offsets. 9:0 119 [9:0] 0x035 valid pixel data (img). the data on the data output channels is valid pixel data (part of the image). 9:0 125 [9:0] 0x059 crc value. the data on the data output channels is the crc code of the finished image data line. 9:0 126 [9:0] 0x3a6 training pattern (tr). the sync channel sends out the training pattern which can be programmed by a register setting.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 40 training patterns on data channels during idle periods, the data channels transmit training patterns, indicated on the sync channel by a tr code. these training patterns are configurable independent of the training code on the sync channel as shown in table 26. table 26. training code on sync channel sync word bit position register address default value description [9:0] 116 [9:0] 0x3a6 data channel training pattern. the data output channels send out the training pattern, which can be programmed by a register setting. the default value of the training pattern is 0x3a6, which is identical to the training pattern indication code on the sync channel. cyclic redundancy code at the end of each line, a crc code is calculated to allow error detection at the receiving end. each data channel transmits a crc code to protect the data words sent during the previous cycles. idle and training patterns are not included in the calculation. the sync channel is not protected. a special character (crc indication) is transmitted whenever the data channels send their respective crc code. the polynomial is x 10 +x 9 +x 6 +x 3 +x 2 +x+1. the crc encoder is seeded at the start of a new line and updated for every (valid) data word received. the crc seed is configurable usign the crc_seed register. when ?0?, the crc is seeded by all-?0?; when ?1? it is seeded with all-?1?. note: note the crc is calculated for every line. this implies that the crc code can protect lines from multiple windows. black reference the sensor reads out one or more black lines at the start of every new frame. the number of black lines to be generated is programmable and is at a minimum, equal to 1. the length of the black lines depends on the operation mode. for global shutter mode, the sensor always reads out the entire line, independent of window configurations. the black references are used to perform black calibration and offset compensation in the data channels. the raw black pixel data is transmitted over the usual lvds channels, while the regular image data is compensated (can be bypassed). on the output interface, black lines can be seen as a separate window, without frame start and ends (only line start and ends). the window id is to be ignored and data is indicated by a bl code.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 41 example using multiple windowing figure 34 shows an example of the synchronization codes sent when reading out multiple windows. figure 34. synchronization codes for multiple windows (applicable for global shutter only) roi0 ls+dc+blx156+le+dc+crc fs+0+imgx(x_size0-4)+le+0+crc ls+0+imgx(x_size0-4)+le+0+crc ls+0+imgx(x_size0-4)+fe+0+crc roi0 roi1 fs+0+imgx(x_size0-4)+le+0+crc ls+0+imgx(x_size0-4)+le+0+fs+1+imgx(x_size1-4)+le+1+crc ls+0+imgx(x_size0-4)+le+0+ls+1+imgx(x_size1-4)+le+1+crc ls+0+imgx(x_size0-4)+le+0+ls+1+imgx(x_size1)+fe+1+crc ls+0+imgx(x_size0-4)+le+0+crc ls+0+imgx(x_size0-4)+fe+0+crc ls+dc+blx156+le+dc+crc ls+0+imgx(x_size0-4)+le+0+crc roi0 roi1 fs+0+imgx(x_size0-4)+le+0+crc ls+0+imgx(x_size0-overlap1_0-2)+fs+1+imgx(x_size1-4)+le+1+crc ls+0+imgx(x_size0-overlap1_0-2)+ls+1+imgx(x_size1-4)+le+1+crc ls+0+imgx(x_size0-overlap1_0-2)+ls+1+imgx(x_size1-4)+le+1+crc ls+1+imgx(x_size1-4)+le+1+crc ls+1+imgx(x_size1-4)+fe+1+crc ls+dc+blx156+le+dc+crc ls+0+imgx(x_size0-4)+le+0+crc where x_size0 = x_end0 - x_start0 + 1 x_size1 = x_end1 - x_start1 + 1 overlap1_0 = x_end0 - x_start1 +1 dc = don't care" roi0 roi1 fs+0+imgx(x_size0-4)+le+0+crc ls+0+imgx(x_size0-4)+le+0+fs+1+imgx(x_size1-4)+le+1+crc ls+0+imgx(x_size0-4)+le+0+ls+1+imgx(x_size1-4)+le+1+crc ls+0+imgx(x_size0-4)+le+0+ls+1+imgx(x_size1-4)+fe+1+crc ls+0+imgx(x_size0-4)+le+0+crc ls+0+imgx(x_size0-4)+fe+0+crc ls+dc+blx156+le+dc+crc ls+0+imgx(x_size0-4)+le+0+crc where x_size0 = x_end0 - x_start0 + 1 x_size1 = x_end1 - x_start1 + 1 dc = don't care" where x_size0 = x_end0 - x_start0 + 1 x_size1 = x_end1 - x_start1 + 1 dc = don't care" where x_size0 = x_end0 - x_start0 + 1 dc = don't care"
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 42 lvds output multiplexin g the python sensor contains a function for down?multiplexing the output channels. using this function, one may for instance use the python xk with 16, 8 or 4 datachannels instead of 32 data channels. enabling the down?multiplexing is done through the muxmode[1:0] pins. connecting these pins to ground disables all down?multiplexing. configuring higher values sets a higher degree of down?multiplexing. the channels that are used per degree of multiplexing are shown in table 27. the unused data channels are powered down and will not send any data. note the maximum frequency for the spi interface needs to scale with the amount of lvds channels as described in table 5. table 27. lvds channel multiplexing no. of lvds outputs channels multiplexed output channel no. of repetition of sync codes 32 no multiplexing ch0 to ch31 1 16 ch0, ch1 ch0 2 ch2, ch3 ch2 ch4, ch5 ch4 ch6, ch7 ch6 ch8, ch9 ch8 ch10, ch11 ch10 ch12, ch13 ch12 ch14, ch15 ch14 ch16, ch17 ch16 ch18, ch19 ch18 ch20, ch21 ch20 ch22, ch23 ch22 ch24, ch25 ch24 ch26, ch27 ch26 ch28, ch29 ch28 ch30, ch31 ch30 8 ch0, ch1, ch2, ch3 ch0 4 ch4, ch5, ch6, ch7 ch4 ch8, ch9, ch10, ch11 ch8 ch12, ch13, ch14, ch15 ch12 ch16, ch17, ch18, ch19 ch16 ch20, ch21, ch22, ch23 ch20 ch24, ch25, ch26, ch27 ch24 ch28, ch29, ch30, ch31 ch28 4 ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7 ch0 8 ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ch8 ch16, ch17, ch18, ch19, ch20, ch21, ch22, ch23 ch16 ch24, ch25, ch26, ch27, ch28, ch29, ch30, ch31 ch24 table 28 shows how to select the desired output multiplex mode and describes the required register upload needed to guarantee the correct functionality of the sensor. table 28. output multiplex mode selection muxmode 1 (pin f24) muxmode 0 (pin f25) number o f output lvds channels required upload address data 0 0 32 211 0x0e5b 0 3.3 v 16 211 0x0e4b 3.3 v 0 8 211 0x0e3b 3.3 v 3.3 v 4 211 0x0e2b
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 43 data order to read out the image data through the output channels, the pixel array is organized in kernels. the kernel size is 64 pixels in x-direction by one pixel in y-direction. figure 35 indicates how the kernels are organized. the data order of this image data on the data output channels depends on the subsampling mode. figure 35. kernel organization in pixel array roi kernel (0,0) kernel (79,5119) kernel (x_start,y_start) 0 63 3 2 1 61 62 pixel array ? p1?se/sn/fn: subsampling disabled ? 32 lvds output channels the image data is read out in kernels of 64 pixels in x-direction by one pixel in y-direction. one data channel output delivers two pixel values of one kernel sequentially. figure 36 shows how a kernel is read out over the 32 output channels. for even positioned kernels, the kernels are read out ascending, and for odd positioned kernels the data order is reversed (descending). figure 36. 32 lvds data output order when subsampling is disabled kernel n?2 kernel n+1 kernel n kernel n?1 0 4 3 2 1 59 63 62 61 60 pixel # (even kernel) channel #0 channel #1 channel #31 channel #30 63 59 60 61 62 4 0 1 2 3 pixel # (odd kernel) 10?bit 10?bit msb lsb msb lsb note: the bit order is always msb first ? 16 lvds output channels figure 37 shows how a kernel is read out over the 16 output channels. each pair of adjacent channels is multiplexed into one channel. for even positioned kernels, the kernels are read out ascending but in pair of even and odd pixels, while for odd positioned kernles the data order is reversed (descending) but in pair of even and odd pixels.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 44 figure 37. data output order for 16 lvds outputs when subsampling is disabled kernel n?2 kernel n+1 kernel n kernel n?1 0 4 3 1 2 59 63 61 62 60 pixel # (even kernel) channel #0 channel #2 channel #30 channel #28 63 59 60 62 61 4 0 2 1 3 pixel # (odd kernel) 10?bit 10?bit msb lsb msb lsb note: the bit order is always msb first, regardless the kernel number 6 7 5 57 56 58 56 57 58 7 6 5 every 2 nd channel ? 8 lvds output channels figure 38 shows how a kernel is read out over the 8 output channels. each bunch of four adjacent channels is multiplexed into one channel. for even positioned kernels, the kernels are read out ascending but in sets of 4 even and 4 odd pixels, while for odd positioned kernles the data order is reversed (descending) but in sets of 4 odd and 4 even pixels. figure 38. data output order for 8 lvds outputs when subsampling is disabled kernel n?2 kernel n+1 kernel n kernel n?1 8 9 14 12 10 62 6 3 61 59 57 channel #0 channel #4 channel #28 channel #24 55 54 49 51 53 1 0 2 4 6 10?bit 10?bit msb lsb msb lsb note: the bit order is always msb first, regardless the kernel number 11 15 13 52 48 50 56 60 58 7 3 5 0 1 6 4 2 63 62 57 59 61 3 7 5 60 56 58 54 55 53 51 49 9 8 10 12 14 48 52 50 15 11 13 p ixel # ( even kernel) p ixel # ( odd kernel) every 4 th channel ? 4 lvds output channels figure 39 shows how a kernel is read out over the 4 output channels. each bunch of eight adjacent channels is multiplexed into one channel. for even positioned kernels, the kernels are read out ascending but in sets of 8 even and 8 odd pixels, while for odd positioned kernles the data order is reversed (descending) but in sets of 8 odd and 8 even pixels.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 45 figure 39. data output order for 4 lvds outputs when subsampling is disabled kernel n?2 kernel n+1 kernel n kernel n?1 1 9 7 5 3 55 6 3 61 59 57 channel #0 channel #24 62 54 56 58 60 8 0 2 4 6 10?bit 10?bit msb lsb msb lsb note: the bit order is always msb first, regardless the kernel number 11 15 13 52 48 50 49 53 51 14 10 12 0 8 6 4 2 63 55 57 59 61 10 14 12 53 49 51 54 62 60 58 56 9 1 3 5 7 48 52 50 15 11 13 pixel # (even kernel) pixel # (odd kernel) every 8 th channel ? subsampling on monochrome sensors during subsampling, every other pixel is read out and the lines are read in a read-1-skip-1 manner. to read out the image data with subsampling enabled, two neighboring kernels are combined to a single kernel of 128 pixels in the x-direction and one pixel in the y-direction. note that there is no difference in data order for even and odd kernel numbers. this is opposed to the ?no-subsampling? readout described earlier. ? 32 lvds output channels figure 40 shows the data order for 32 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in section 0. figure 40. data output order for 32 lvds output channels in subsampling mode on a monochrome sensor kernel n?2 kernel n+1 kernel n kernel n?1 0 4 124 2 126 68 64 62 66 60 pixel # channel #0 channel #1 channel #31 channel #30
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 46 ? 16 lvds output channels figure 41 shows the data order for 16 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in section 0. figure 41. data output order for 16 lvds output channels in subsampling mode on a monochrome sensor kernel n?2 kernel n+1 kernel n kernel n?1 0 4 124 126 2 68 64 66 62 60 pixel # channel #0 channel #2 channel #30 channel #28 6 120 122 56 70 58 every 2 nd channel ? 8 lvds output channels figure 42 shows the data order for 8 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in section 0. figure 42. data output order for 8 lvds output channels in subsampling mode on a monochrome sensor kernel n?2 kernel n+1 kernel n kernel n?1 8 118 14 12 10 62 64 66 68 70 p ixel # channel #0 channel #4 channel #28 channel #24 116 112 114 56 60 58 0 126 6 4 2 124 120 122 54 72 74 76 78 48 52 50 every 4 th channel ? 4 lvds output channels figure 43 shows the data order for 4 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in section 0. figure 43. data output order for 4 lvds output channels in subsampling mode on a monochrome sensor kernel n?2 kernel n+1 kernel n kernel n?1 126 118 120 122 124 72 64 66 68 70 channel #0 channel #24 116 112 114 78 74 76 0 8 6 4 2 10 14 12 54 62 60 58 56 48 52 50 every 8 th channel ? binning mode the output order in binning mode is identical to the subsampled mode. ? subsampling on color sensor to read out the image data with subsampling enabled on a color sensor, two neighboring kernels are combined to a single kernel of 128 pixels in the x-direction and 1 pixel in the y-direction. only the pixels 0, 1, 4, 5, 8, 9, 12, 13 to 124, and 125 are read out. there is no difference in data order for even/odd kernel numbers, as opposed to the ?no-subsampling? readout described in section. ? 32 lvds output channels figure 44 shows the data order for 32 lvds output channels.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 47 figure 44. data output order for 32 lvds output channels in subsampling mode on a color sensor kernel n?2 kernel n+1 kernel n kernel n?1 0 4 124 125 1 68 64 65 66 60 pixel # channel #0 channel #1 channel #31 channel #30 120 121 5 channel #2 channel #3 56 69 57 channel #29 channel #28 ? 16 lvds output channels figure 45 shows the data order for 16 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in section 0. figure 45. data output order for 16 lvds output channels in subsampling mode on a color sensor kernel n?2 kernel n+1 kernel n kernel n?1 0 4 124 1 125 68 64 61 65 60 pixel # channel #0 channel #2 channel #30 channel #28 121 120 5 56 57 69 every 2 nd channel ? 8 lvds output channels figure 46 shows the data order for 8 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in section 0. figure 46. data output order for 8 lvds output channels in subsampling mode on a color sensor kernel n?2 kernel n+1 kernel n kernel n?1 8 9 113 12 117 65 64 61 68 57 pixel # channel #0 channel #4 channel #28 channel #24 116 112 13 56 60 69 0 1 121 4 125 124 120 5 73 72 53 76 49 48 52 77 every 4 th channel ? 4 lvds output channels figure 47 shows the data order for 4 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in section 0.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 48 figure 47. data output order for 4 lvds output channels in subsampling mode on a color sensor kernel n?2 kernel n+1 kernel n kernel n?1 1 9 120 5 124 72 64 61 68 57 channel #0 channel #24 116 112 13 49 53 76 0 8 121 4 125 117 113 12 73 65 60 69 56 48 52 77 every 8 th channel frame rate frame rate for subsampling and binning mode is compared to the normal mode. assume the y-resolution is the programmed number of lines to read out. normal readout the frame time in normal readout mode is shown by the following formula: frame time = t fot + (y-resolution) x (t rot + t readout ) the frame rate is equal to 1/frametime. nominal frame rate for full frame readout is 80 fps in zero?rot mode. subsampling mode the frame time for subsampled readout is shown by the following formula: frame t ime = t fot + (y-resolution / 2) x (t rot + t readout / 2), where t rot represents the equivalent rot time for a normal readout of the same frame. analogous readout represents the equivalent readout time for normal readout. binning mode the frame time for subsampled readout is given by the following formula: frame time = t fot + (y-resolution / 2) x (t rot x 2+ t readout / 2), where t rot represents the equivalent rot time for a normal readout of the same frame. analogous readout represents the equivalent readout time for normal readout. test pattern generation the data block provides several test pattern generation capabilities. figure 48 shows the functional diagram for the data channels. it is possible to inject synthesized test patterns at various points. refer to the register map on page 50 for the test mode configuration registers (registers 144 to 150). the test pattern modes are summarized in table 29. note that these modes only exist for the data channel. the sync and clock channels do not provide this functionality. for each test mode, the user can select whether the generated data is framed. when the register frame_testpattern is asserted, the test data simply replaces the adc data. this means that the test data is only sent between frame/line start and frame/line end indications. outside these windows, regular training patterns are sent, as during normal operation. crc is calculated and inserted as for normal data for the fixed and incrementing test pattern generation. table 29. test mode summary register configuration description prbs_en testpattern_en testpattern 0 0 x normal operation mode 0 1 0 fixed pattern generation. pattern is defined by testpattern register 0 1 1 incrementing pattern generation. initial value is determined by testpattern . 1 x x prbs data generation. the testpattern register determines the seed for the prbs generator. when frame_testpattern is deasserted, the output is constantly replaced by the generated test data. no training patterns are generated.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 49 figure 48. functional block diagrams for the data channels ( testpattern_en and not frame_testpattern ) `1' `0' testpattern_er `0' `1' training pattern insert crc `0' `1' bypass prbs_en adc_db_data_0 black leve l calibration adc_db_data_1 `1' `0' `0' `1' ? black leve l calibration test pattern generation prbs generator crc calculation note: in the figure, register configurations are indicated in red. the sync channel continues to send regular frame timing information when the sequencer is enabled (independently of the test pattern configurations). the synthesized test patterns are injected directly into the data channels. therefore, no data demultiplexing is required at the receiving end (as opposed to regular image data capture). fixed pattern a configured word can be continuously repeated on the output. this word is configurable for each data channel separately (testpattern). the testpattern is inserted when testpattern_en is asserted. incrementing test pattern in each cycle, the test pattern word is incremented by one, when inc_testpattern is asserted. after reaching the maximum value, the incrementer is reset to its start value (testpattern). when the testdata is framed, the incrementer is also reset to the testpattern value at each line start. to enable this mode, enable the digital testpattern mode (assert testpattern_en) and assert inc_testpattern. pseudo random bit sequence generation in this test mode, the output channels are sourced with pseudo random bit sequence (prbs) pattern. the prbs seed can be configured for each data channel using the testpattern register. for the other test pattern generation mode, the datastream is not interrupted when frame_testpattern is deasserted. notes: ? the crc generator is not functional in this mode, and no real crc can be calculated. instead, the crc slot is used to send one more prbs word. ? a prbs generator does not generate random data when the seed is all zero. therefore, it is advisable to configure the testpattern registers to a value different from ?0?. using different seeds for each channel results in different sequences for each data channel.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 50 register map each functional entity has a dedicated address space, starting at a block of fset. the register address is obtained by adding the address offset to the block offset. this address must be used to perform spi uploads and is shown in the address column of the register map table. the table below represents the register map for the noip1xx025ka part. deviating default values for the noip1xx16ka, noip1xx12ka and noip1xx10ka are mentioned between brackets (?[]?). table 30. register map category block offset address offset address bit field register name default (hex) default description type chip id 0 0 0 chip_id 0x50fa 20730 chip id status [15:0] id 0x50fa 20730 chip id 1 1 reserved 0x0000 0 reserved status [3:0] reserved 0x0 0 reserved [9:8] resolution 0x0 0 p25k: 0, p16k: 1, p12k: 2, p10k: 3 [11:10] reserved 0x0 0 reserved 2 2 chip_configuration 0x0000 0 chip general configuration rw [0] color 0x0 0 color/monochrome configuration ?0?: monochrome ?1?: color [1] reserved 0x0 0 reserved [15:2] reserved 0x0 0 reserved reset gen- erator 8 0 8 reserved 0x0099 153 reserved rw [3:0] reserved 0x9 9 reserved [7:4] reserved 0x9 9 reserved 1 9 reserved 0x0009 9 reserved rw [3:0] reserved 0x9 9 reserved 2 10 reserved 0x0999 2457 reserved rw [3:0] reserved 0x9 9 reserved [7:4] reserved 0x9 9 reserved [11:8] reserved 0x9 9 reserved 16 reserved reserved 0 16 reserved 0x0004 4 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x1 1 reserved 1 17 reserved 0x2113 8467 reserved rw [7:0] reserved 0x13 19 reserved [12:8] reserved 0x1 1 reserved [14:13] reserved 0x1 1 reserved 20 reserved reserved 0 20 reserved 0x0000 0 reserved rw [0] reserved 0x0 0 reserved [9:8] reserved 0x0 0 reserved [10] reserved 0x0 0 reserved 24 reserved reserved 0 24 reserved 0x0000 0 reserved status [0] reserved 0x0 0 reserved
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 51 table 30. register map category type description default default (hex) register name bit field address address offset block offset 2 26 reserved 0x2280 8832 reserved rw [7:0] reserved 0x80 128 reserved [10:8] reserved 0x2 2 reserved [14:12] reserved 0x2 2 reserved 3 27 reserved 0x3d2d 15661 reserved rw [7:0] reserved 0x2d 45 reserved [15:8] reserved 0x3d 61 reserved clock gen- erator 32 0 32 config0 0x0004 4 clock generator config- uration rw [0] enable_analog 0x0 0 enable analogue clocks ?0?: disabled, ?1?: enabled [1] reserved 0x0 0 reserved [2] reserved 0x1 1 reserved [3] reserved 0x0 0 reserved [5:4] mux 0x0 0 multiplex mode [11:8] reserved 0x0 0 reserved [14:12] reserved 0x0 0 reserved general logic 34 0 34 config0 0x0000 0 clock generator config- uration rw [0] enable 0x0 0 logic general enable configuration ?0?: disable ?1?: enable 38 0 38 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 1 39 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved image core 40 0 40 image_core_config0 0x0000 0 image core configuration rw [0] imc_pwd_n 0x0 0 image core power down ?0?: powered down, ?1?: powered up [1] mux_pwd_n 0x0 0 column multiplexer power down ?0?: powered down, ?1?: powered up [2] colbias_enable 0x0 0 bias enable ?0?: disabled ?1?: enabled 1 41 reserved 0x0b5a 2906 reserved rw [3:0] reserved 0xa 10 reserved [7:4] reserved 0x5 5 reserved [10:8] reserved 0x3 3 reserved [12:11] reserved 0x1 1 reserved [13] reserved 0x0 0 reserved [14] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 2 42 reserved 0x0001 1 reserved rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 52 table 30. register map category type description default default (hex) register name bit field address address offset block offset [0] reserved 0x1 1 reserved [1] reserved 0x0 0 reserved [6:4] reserved 0x0 0 reserved [10:8] reserved 0x0 0 reserved [15:12] reserved 0x0 0 reserved 3 43 reserved 0x0000 0 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [6:4] reserved 0x0 0 reserved [7] reserved 0x0 0 reserved [15:8] reserved 0x0 0 reserved afe 48 0 48 power_down 0x0000 0 afe configuration rw [0] pwd_n 0x0 0 power down for afe?s ?0?: powered down, ?1?: powered up bias 64 0 64 power_down 0x0000 0 bias power down con- figuration rw [0] pwd_n 0x0 0 power down bandgap ?0?: powered down, ?1?: powered up 1 65 configuration 0x888b 34955 bias configuration rw [0] extres 0x1 1 external resistor selection ?0?: internal resistor, ?1?: external resistor [3:1] reserved 0x5 5 reserved [7:4] reserved 0x8 8 reserved [11:8] reserved 0x8 8 reserved [15:12] reserved 0x8 8 reserved 2 66 reserved 0x53c8 21448 reserved rw [3:0] reserved 0x8 8 reserved [7:4] reserved 0xc 12 reserved [14:8] reserved 0x53 83 reserved 3 67 reserved 0x8888 34952 reserved rw [3:0] reserved 0x8 8 reserved [7:4] reserved 0x8 8 reserved [11:8] reserved 0x8 8 reserved [15:12] reserved 0x8 8 reserved 4 68 lvds_bias 0x0088 136 lvds bias configuration rw [3:0] lvds_ibias 0x8 8 lvds ibias [7:4] lvds_iref 0x8 8 lvds iref 5 69 reserved 0x0888 2184 reserved rw [3:0] reserved 0x8 8 reserved [7:4] reserved 0x8 8 reserved [11:8] reserved 0x8 8 reserved 6 70 reserved 0x8888 34952 reserved rw [3:0] reserved 0x8 8 reserved
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 53 table 30. register map category type description default default (hex) register name bit field address address offset block offset [7:4] reserved 0x8 8 reserved [11:8] reserved 0x8 8 reserved [15:12] reserved 0x8 8 reserved 7 71 reserved 0x8888 34952 reserved rw [15:0] reserved 0x8888 34952 reserved 72 reserved reserved 0 72 reserved 0x2220 8736 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [6:4] reserved 0x2 2 reserved [10:8] reserved 0x2 2 reserved [14:12] reserved 0x2 2 reserved 80 reserved reserved 0 80 reserved 0x0000 0 reserved rw [1:0] reserved 0x0 0 reserved [3:2] reserved 0x0 0 reserved [5:4] reserved 0x0 0 reserved [7:6] reserved 0x0 0 reserved [9:8] reserved 0x0 0 reserved 1 81 reserved 0x8881 34945 reserved rw [15:0] reserved 0x8881 34945 reserved tempera- ture sensor 96 0 96 enable 0x0000 0 temperature sensor configuration rw [0] enable 0x0 0 temperature diode enable ?0?: disabled, ?1?: enabled [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] reserved 0x0 0 reserved [5] reserved 0x0 0 reserved [13:8] offset 0x0 0 temperature offset (signed) 1 97 temp 0x0000 0 temperature sensor status status [7:0] temp 0x00 0 temperature readout 104 reserved reserved 0 104 reserved 0x0000 0 reserved rw [15:0] reserved 0x0 0 reserved 1 105 reserved 0x0000 0 reserved rw [1:0] reserved 0x0 0 reserved [6:2] reserved 0x0 0 reserved [7] reserved 0x0 0 reserved [9:8] reserved 0x0 0 reserved [14:10] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 2 106 reserved 0x0000 0 reserved status
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 54 table 30. register map category type description default default (hex) register name bit field address address offset block offset [15:0] reserved 0x0000 0 reserved 3 107 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 4 108 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 5 109 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 6 110 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 7 111 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved serializers/ lvds/io 112 0 112 power_down 0x0000 0 lvds power down con- figuration rw [0] clock_out_pwd_n 0x0 0 power down for clock output. ?0 ?: powered down, ?1?: powered up [1] sync_pwd_n 0x0 0 power down for sync channel ?0?: powered down, ?1?: powered up [2] data_pwd_n 0x0 0 power down for data channels (4 channels) ?0?: powered down, ?1?: powered up sync words 116 4 116 trainingpattern 0x03a6 934 data formating ? training pattern rw [9:0] trainingpattern 0x3a6 934 training pattern sent on data channels during idle mode. this data is used to perform word alignment on the lvds data channels. 5 117 sync_code0 0x002a 42 lvds power down con- figuration rw [6:0] frame_sync_0 0x02a 42 frame sync code lsbs ? even kernels 6 118 sync_code1 0x0015 21 data formating ? bl in- dication rw [9:0] bl_0 0x015 21 black pixel identification sync code ? even kernels 7 119 sync_code2 0x0035 53 data formating ? img indication rw [9:0] img_0 0x035 53 valid pixel identification sync code ? even kernels 8 120 sync_code3 0x0025 37 data formating ? img indication rw [9:0] ref_0 0x025 37 reference pixel identifi- cation sync code ? even kernels 9 121 sync_code4 0x002a 42 lvds power down con- figuration rw [6:0] frame_sync_1 0x02a 42 frame sync code lsbs ? odd kernels 10 122 sync_code5 0x0015 21 data formating ? bl in- dication rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 55 table 30. register map category type description default default (hex) register name bit field address address offset block offset [9:0] bl_1 0x015 21 black pixel identification sync code ? odd kernels 11 123 sync_code6 0x0035 53 data formating ? img indication rw [9:0] img_1 0x035 53 valid pixel identification sync code ? odd kernels 12 124 sync_code7 0x0025 37 data formating ? img indication rw [9:0] ref_1 0x025 37 reference pixel identifi- cation sync code ? odd kernels 13 125 sync_code8 0x0059 89 data formating ? crc indication rw [9:0] crc 0x059 89 crc value identification sync code 14 126 sync_code9 0x03a6 934 data formating ? tr in- dication rw [9:0] tr 0x3a6 934 training value identifica- tion sync code 15 127 reserved 0x02aa 682 reserved rw [9:0] reserved 0x2aa 682 reserved data block 128 0 128 blackcal 0x4008 16392 black calibration config- uration rw [7:0] black_offset 0x08 8 desired black level at output [10:8] black_samples 0x0 0 black pixels taken into account for black calibration. total samples = 2**black_samples [14:11] reserved 0x8 8 reserved [15] crc_seed 0x0 0 crc seed ?0?: all?0 ?1?: all?1 1 129 general_configuration 0x0001 1 black calibration and data formating configuration rw [0] auto_blackcal_enable 0x1 1 automatic blackcalibration is enabled when 1, bypassed when 0 [9:1] blackcal_offset 0x00 0 black calibration offset used when au- to_black_cal_en = ?0?. [10] blackcal_offset_dec 0x0 0 blackcal_offset is added when 0, subtracted when 1 [11] reserved 0x0 0 reserved [12] reserved 0x0 0 reserved [13] reserved 0x0 0 reserved [14] ref_mode 0x0 0 data contained on reference lines: ?0?: reference pixels ?1?: black average for the corresponding data channel [15] ref_bcal_enable 0x0 0 enable black calibration on reference lines ?0?: disabled ?1?: enabled
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 56 table 30. register map category type description default default (hex) register name bit field address address offset block offset 2 130 reserved 0x000f 15 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x1 1 reserved [2] reserved 0x1 1 reserved [3] reserved 0x1 1 reserved [4] reserved 0x0 0 reserved [8] reserved 0x0 0 reserved 8 136 blackcal_error0 0x0000 0 black calibration status status [15:0] blackcal_error[15:0] 0x0000 0 black calibration error. this flag is set when not enough black samples are availlable. black calibration shall not be valid. channels 0?16 9 137 blackcal_error1 0x0000 0 black calibration status status [15:0] blackcal_error[31:16] 0x0000 0 black calibration error. this flag is set when not enough black samples are availlable. black calibration shall not be valid. channels 16?31 10 138 blackcal_error2 0x0000 0 black calibration status status [15:0] blackcal_error[47:32] 0x0000 0 black calibration error. this flag is set when not enough black samples are availlable. black calibration shall not be valid. channels 32?47 11 139 blackcal_error3 0x0000 0 black calibration status status [15:0] blackcal_error[63:48] 0x0000 0 black calibration error. this flag is set when not enough black samples are availlable. black calibration shall not be valid. channels 48?63 12 140 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 13 141 reserved 0xffff 65535 reserved rw [15:0] reserved 0xffff 65535 reserved 16 144 test_configuration 0x0000 0 data formating test configuration rw [0] testpattern_en 0x0 0 insert synthesized test- pattern when ?1? [1] inc_testpattern 0x0 0 incrementing testpattern when ?1?, constant test- pattern when ?0? [2] prbs_en 0x0 0 insert prbs when ?1? [3] frame_testpattern 0x0 0 frame test patterns when ?1?, unframed testpatterns when ?0? [4] reserved 0x0 0 reserved 17 145 reserved 0x0000 0 reserved rw [15:0] reserved 0 reserved 18 146 test_configuration0 0x0100 256 data formating test configuration rw [7:0] testpattern0_lsb 0x00 0 testpattern used on datapath #0 when testpattern_en = ?1?. note: most significant bits are configured in register 150.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 57 table 30. register map category type description default default (hex) register name bit field address address offset block offset [15:8] testpattern1_lsb 0x01 1 testpattern used on datapath #1 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 19 147 test_configuration1 0x0302 770 data formating test configuration rw [7:0] testpattern2_lsb 0x02 2 testpattern used on datapath #2 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern3_lsb 0x03 3 testpattern used on datapath #3 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 20 148 test_configuration2 0x0504 1284 data formating test configuration rw [7:0] testpattern4_lsb 0x04 4 testpattern used on datapath #4 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern5_lsb 0x05 5 testpattern used on datapath #5 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 21 149 test_configuration3 0x0706 1798 data formating test configuration rw [7:0] testpattern6_lsb 0x06 6 testpattern used on datapath #6 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern7_lsb 0x07 7 testpattern used on datapath #7 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 22 150 test_configuration16 0x0000 0 data formating test configuration rw [1:0] testpattern0_msb 0x0 0 testpattern used when testpattern_en = ?1? [3:2] testpattern1_msb 0x0 0 testpattern used when testpattern_en = ?1? [5:4] testpattern2_msb 0x0 0 testpattern used when testpattern_en = ?1? [7:6] testpattern3_msb 0x0 0 testpattern used when testpattern_en = ?1? [9:8] testpattern4_msb 0x0 0 testpattern used when testpattern_en = ?1? [11:10] testpattern5_msb 0x0 0 testpattern used when testpattern_en = ?1? [13:12] testpattern6_msb 0x0 0 testpattern used when testpattern_en = ?1? [15:14] testpattern7_msb 0x0 0 testpattern used when testpattern_en = ?1? 26 154 reserved 0x0000 0 reserved rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 58 table 30. register map category type description default default (hex) register name bit field address address offset block offset [15:0] reserved 0x0000 0 reserved 27 155 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 160 reserved reserved 0 160 reserved 0x0010 16 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] reserved 0x1 1 reserved 1 161 reserved 0x60b8 24760 reserved rw [9:0] reserved 0xb8 184 reserved [15:10] reserved 0x018 24 reserved 2 162 reserved 0x0080 128 reserved rw [9:0] reserved 0x80 128 reserved 3 163 reserved 0x0080 128 reserved rw [9:0] reserved 0x80 128 reserved 4 164 reserved 0x0080 128 reserved rw [9:0] reserved 0x80 128 reserved 5 165 reserved 0x0080 128 reserved rw [9:0] reserved 0x80 128 reserved 6 166 reserved 0x03ff 1023 reserved rw [15:0] reserved 0x03ff 1023 reserved 7 167 reserved 0x0800 2048 reserved rw [1:0] reserved 0x0 0 reserved [3:2] reserved 0x0 0 reserved [15:4] reserved 0x080 128 reserved 8 168 reserved 0x0001 1 reserved rw [15:0] reserved 0x0001 1 reserved 9 169 reserved 0x0800 2048 reserved rw [1:0] reserved 0x0 0 reserved [3:2] reserved 0x0 0 reserved [15:4] reserved 0x080 128 reserved 10 170 reserved 0x03ff 1023 reserved rw [15:0] reserved 0x03ff 1023 reserved 11 171 reserved 0x100d 4109 reserved rw [1:0] reserved 0x1 1 reserved [3:2] reserved 0x3 3 reserved [15:4] reserved 0x100 256 reserved 12 172 reserved 0x0083 131 reserved rw [7:0] reserved 0x083 131 reserved [13:8] reserved 0x00 0 reserved [15:14] reserved 0x0 0 reserved 13 173 reserved 0x2824 10276 reserved rw [7:0] reserved 0x024 36 reserved [15:8] reserved 0x028 40 reserved 14 174 reserved 0x2a96 10902 reserved rw [3:0] reserved 0x6 6 reserved
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 59 table 30. register map category type description default default (hex) register name bit field address address offset block offset [7:4] reserved 0x9 9 reserved [11:8] reserved 0xa 10 reserved [15:12] reserved 0x2 2 reserved 15 175 reserved 0x0080 128 reserved rw [9:0] reserved 0x080 128 reserved 16 176 reserved 0x0100 256 reserved rw [9:0] reserved 0x100 256 reserved 17 177 reserved 0x0100 256 reserved rw [9:0] reserved 0x100 256 reserved 18 178 reserved 0x0080 128 reserved rw [9:0] reserved 0x080 128 reserved 19 179 reserved 0x00aa 170 reserved rw [9:0] reserved 0x0aa 170 reserved 20 180 reserved 0x0100 256 reserved rw [9:0] reserved 0x100 256 reserved 21 181 reserved 0x0155 341 reserved rw [9:0] reserved 0x155 341 reserved 24 184 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 25 185 reserved 0x0000 0 reserved status [7:0] reserved 0x0 0 reserved 26 186 reserved 0x0000 0 reserved status [9:0] reserved 0x000 0 reserved [12] reserved 0x0 0 reserved 27 187 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 28 188 reserved 0x0000 0 reserved status [1:0] reserved 0x0 0 reserved [3:2] reserved 0x0 0 reserved [15:4] reserved 0x000 0 reserved 29 189 reserved 0x0000 0 reserved status [12:0] reserved 0x000 0 reserved [13] reserved 0x0 0 reserved sequencer 192 0 192 general_configuration 0x0000 0 sequencer general configuration rw [0] enable 0x0 0 enable sequencer ?0?: idle, ?1?: enabled [1] reserved 0x0 0 reserved [2] zero_rot_enable 0x0 0 zero rot mode selection. ?0?: normal rot, ?1?: zero rot? [3] reserved 0x0 0 reserved [4] triggered_mode 0x0 0 triggered mode selection ?0?: normal mode, ?1?: triggered mode [5] slave_mode 0x0 0 master/slave selection ?0?: master, ?1?: slave
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 60 table 30. register map category type description default default (hex) register name bit field address address offset block offset [6] nzrot_xsm_delay_en- able 0x0 0 insert delay between end of rot and start of readout in normal rot readout mode if ?1?. rot delay is defined by register xsm_delay [7] subsampling 0x0 0 subsampling mode selection ?0?: no subsampling, ?1?: subsampling [8] binning 0x0 0 binning mode selection ?0?: no binning, ?1?: binning [10] reserved 0x0 0 reserved [13:11] monitor_select 0x0 0 control of the monitor pins [14] reserved 0x0 0 reserved [15] sequence 0x0 0 enable a sequenced readout with different parameters for even and odd frames. 1 193 reserved 0x0000 0 reserved rw [7:0] reserved 0x00 0 reserved [15:8] reserved 0x00 0 reserved 2 194 integration_control 0x00e4 228 integration control rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] fr_mode 0x1 1 representation of fr_length. ?0?: reset length ?1?: frame length [3] reserved 0x0 0 reserved [4] int_priority 0x0 0 integration priority ?0?: frame readout has priority over integration ?1?: integration end has priority over frame read- out [5] halt_mode 0x1 1 the current frame will be completed when the sequencer is disabled and halt_mode = ?1?. when ?0?, the sensor stops immediately when disabled, without fin- ishing the current frame. [6] fss_enable 0x1 1 generation of frame sequence start sync code (fss) ?0?: no generation of fss ?1?: generation of fss [7] fse_enable 0x1 1 generation of frame sequence end sync code (fse) ?0?: no generation of fse ?1?: generation of fse [8] reverse_y 0x0 0 reverse readout ?0?: bottom to top readout ?1?: top to bottom readout [9] reserved 0x0 0 reserved
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 61 table 30. register map category type description default default (hex) register name bit field address address offset block offset [11:10] subsampling_mode 0x0 0 subsampling mode 0x0: subsampling in x and y (vita compatible) 0x1: subsampling in x, not y 0x2: subsampling in y, not x 0x3: subsampling in x an y [13:12] binning_mode 0x0 0 binning mode 0x0: binning in x and y (vita compatible) 0x1: binning in x, not y 0x2: binning in y, not x 0x3: binning in x an y [14] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 3 195 roi_active0_0 0x0001 1 active roi selection rw [15:0] roi_active0 0x01 1 active roi selection [0] roi0 active [1] roi1 active ... [15] roi15 active 4 196 roi_active1_0 0x0000 0 active roi selection rw [15:0] roi_active1_0 0x0000 0 active roi selection [0] roi16 active [1] roi17 active ... [15] roi31 active 5 197 black_lines 0x0102 258 black line configuration rw [7:0] black_lines 0x02 2 number of black lines. minimum is 1. range 1?255 [12:8] gate_first_line 0x1 1 blank out first lines 0: no blank 1?31: blank 1?31 lines 6 198 reserved 0x0000 0 reserved rw [11:0] reserved 0x000 0 reserved 7 199 mult_timer0 0x0001 1 exposure/frame rate configuration rw [15:0] mult_timer0 0x0001 1 mult timer defines granularity (unit = 1/pll clock) of exposure and re- set_length 8 200 fr_length0 0x0000 0 exposure/frame rate configuration rw [15:0] fr_length0 0x0000 0 frame/reset length reset length when fr_mode = ?0?, frame length when fr_mode = ?1? granularity defined by mult_timer 9 201 exposure0 0x0000 0 exposure/frame rate configuration rw [15:0] exposure0 0x0000 0 exposure time granularity defined by mult_timer 10 202 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 11 203 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 12 204 gain_configuration0 0x01e3 483 gain configuration rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 62 table 30. register map category type description default default (hex) register name bit field address address offset block offset [4:0] mux_gainsw0 0x03 3 column gain setting [12:5] reserved 0xf 15 reserved [13] gain_lat_comp 0x0 0 postpone gain update by 1 frame when ?1? to compensate for expo- sure time updates laten- cy. gain is applied at start of next frame if ?0? 13 205 digital_gain_con- figuration0 0x0080 128 gain configuration rw [11:0] db_gain0 0x080 128 digital gain 14 206 sync_configuration 0x037f 895 synchronization configuration rw [0] sync_rs_x_length 0x1 1 update of rs_x_length will not be sync?ed at start of frame when ?0? [1] sync_black_lines 0x1 1 update of black_lines will not be sync?ed at start of frame when ?0? [2] sync_dummy_lines 0x1 1 update of dummy_lines will not be sync?ed at start of frame when ?0? [3] sync_exposure 0x1 1 update of exposure will not be sync?ed at start of frame when ?0? [4] sync_gain 0x1 1 update of gain settings (gain_sw, afe_gain) will not be sync?ed at start of frame when ?0? [5] sync_roi 0x1 1 update of roi updates (active_roi) will not be sync?ed at start of frame when ?0? [6] sync_ref_lines 0x1 1 update of ref_lines will not be sync?ed at start of frame when ?0? [8] blank_roi_switch 0x1 1 blank first frame after roi switching [9] blank_subsam- pling_ss 0x1 1 blank first frame after subsampling/binning mode switching ?0?: no blanking ?1?: blanking [10] exposure_sync_mode 0x0 0 when ?0?, exposure con- figurations are sync?ed at the start of fot. when ?1?, exposure configura- tions sync is disabled (continuously syncing). this mode is only rele- vant for triggered ? master mode, where the exposure configurations are sync?ed at the start of exposure rather than the start of fot. for all other modes it should be set to ?0?. note: sync is still post- poned if sync_expo- sure=?0?. 15 207 ref_lines 0x0000 0 reference line configu- ration rw [7:0] ref_lines 0x00 0 number of reference lines 0?255 16 208 reserved 0x4f00 20224 reserved rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 63 table 30. register map category type description default default (hex) register name bit field address address offset block offset [7:0] reserved 0x00 0 reserved [15:8] reserved 0x4f 79 reserved 19 211 reserved 0x0e5b 3675 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x1 1 reserved [2] reserved 0x0 0 reserved [3] reserved 0x1 1 reserved [6:4] reserved 0x5 5 reserved [15:8] reserved 0xe 14 reserved 20 212 reserved 0x0000 0 reserved rw [12:0] reserved 0x0000 0 reserved [15] reserved 0x0 0 reserved 21 213 reserved 0x13ff 5119 reserved rw [12:0] reserved 0x13ff 5119 reserved 22 214 reserved 0x0000 0 reserved rw [7:0] reserved 0x00 0 reserved [15:8] reserved 0x0 0 reserved 23 215 reserved 0x0103 259 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x1 1 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] reserved 0x0 0 reserved [5] reserved 0x0 0 reserved [6] reserved 0x0 0 reserved [7] reserved 0x0 0 reserved [8] reserved 0x1 1 reserved [9] reserved 0x0 0 reserved [10] reserved 0x0 0 reserved [11] reserved 0x0 0 reserved [12] reserved 0x0 0 reserved [13] reserved 0x0 0 reserved [14] reserved 0x0 0 reserved 24 216 reserved 0x7f08 32520 reserved rw [6:0] reserved 0x08 8 reserved [14:8] reserved 0x7f 127 reserved 25 217 reserved 0x4444 17476 reserved rw [6:0] reserved 0x44 68 reserved [14:8] reserved 0x44 68 reserved 26 218 reserved 0x4444 17476 reserved rw [6:0] reserved 0x44 68 reserved [14:8] reserved 0x44 68 reserved 27 219 reserved 0x0016 22 reserved rw [6:0] reserved 0x016 22 reserved [14:8] reserved 0x00 0 reserved 28 220 reserved 0x301f 12319 reserved rw [6:0] reserved 0x1f 31 reserved [14:8] reserved 0x30 48 reserved
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 64 table 30. register map category type description default default (hex) register name bit field address address offset block offset 29 221 reserved 0x6245 25157 reserved rw [6:0] reserved 0x45 69 reserved [14:8] reserved 0x62 98 reserved 30 222 reserved 0x6230 25136 reserved rw [6:0] reserved 0x30 48 reserved [14:8] reserved 0x62 98 reserved 31 223 reserved 0x001a 26 reserved rw [6:0] reserved 0x1a 26 reserved 32 224 reserved 0x3e01 15873 reserved rw [3:0] reserved 0x1 1 reserved [7:4] reserved 0x00 0 reserved [8] reserved 0x0 0 reserved [9] reserved 0x1 1 reserved [10] reserved 0x1 1 reserved [11] reserved 0x1 1 reserved [12] reserved 0x1 1 reserved [13] reserved 0x1 1 reserved 33 225 reserved 0x5ef1 24305 reserved rw [4:0] reserved 0x11 17 reserved [9:5] reserved 0x17 23 reserved [14:10] reserved 0x17 23 reserved [15] reserved 0x0 0 reserved 34 226 reserved 0x6000 24576 reserved rw [4:0] reserved 0x00 0 reserved [9:5] reserved 0x00 0 reserved [14:10] reserved 0x18 24 reserved [15] reserved 0x0 0 reserved 35 227 reserved 0x0000 0 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] reserved 0x0 0 reserved 36 228 roi_active0_1 0x0001 1 active roi selection rw [7:0] roi_active1 0x01 1 active roi selection [0] roi0 active [1] roi1 active ... [15] roi15 active 37 229 roi_active1_1 0x0000 0 active roi selection rw [15:0] roi_active1_1 0x0000 0 active roi selection [0] roi16 active [1] roi17 active ... [15] roi31 active 38 230 mult_timer1 0x0001 1 exposure/frame rate configuration rw [15:0] mult_timer1 0x0001 1 mult timer defines granularity (unit = 1/pll clock) of expo- sure and reset_length 39 231 fr_length1 0x0000 0 exposure/frame rate configuration rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 65 table 30. register map category type description default default (hex) register name bit field address address offset block offset [15:0] fr_length1 0x0000 0 frame/reset length reset length when fr_mode = ?0?, frame length when fr_mode = ?1? granularity defined by mult_timer 40 232 exposure1 0x0000 0 exposure/frame rate configuration rw [15:0] exposure1 0x0000 0 exposure time granularity defined by mult_timer 41 233 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 42 234 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 43 235 gain_configuration1 0x01e3 483 gain configuration rw [4:0] mux_gainsw1 0x03 3 column gain setting [12:5] afe_gain1 0xf 15 afe programmable gain setting 44 236 digital_gain_con- figuration1 0x0080 128 gain configuration rw [11:0] db_gain1 0x080 128 digital gain 45 237 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 46 238 reserved 0xffff 65535 reserved rw [15:0] reserved 0xffff 65535 reserved 47 239 reserved 0x0000 0 reserved rw [15:0] reserved 0x0 0 reserved 48 240 x_resolution 0x0050 [0x0042, 0x0042, 0x003e] 80 [66, 66, 62] sequencer status status [7:0] x_resolution 0x0050 [0x0042, 0x0042, 0x003e] 80 [66, 66, 62] sensor x resolution 49 241 y_resolution 0x1400 5120 sequencer status status [12:0] y_resolution 0x1400 [0x1010, 0x0c10, 0x0b60] 5120 [4112, 3088, 2912] sequencer status 50 242 mult_timer_status 0x0000 0 sequencer status status [15:0] mult_timer 0x0000 0 mult timer status (master global shutter only) 51 243 reset_length_status 0x0000 0 sequencer status status [15:0] reset_length 0x0000 0 current reset length (not in slave mode) 52 244 exposure_status 0x0000 0 sequencer status status [15:0] exposure 0x0000 0 current exposure time (not in slave mode) 53 245 exposure_ds_status 0x0000 0 sequencer status status [15:0] exposure_ds 0x0000 0 current exposure time (not in slave mode) 54 246 exposure_ts_status 0x0000 0 sequencer status status [15:0] exposure_ts 0x0000 0 current exposure time (not in slave mode) 55 247 gain_status 0x0000 0 sequencer status status
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 66 table 30. register map category type description default default (hex) register name bit field address address offset block offset [4:0] mux_gainsw 0x00 0 current column gain setting [12:5] afe_gain 0x00 0 current afe program- mable gain 56 248 digital_gain_status 0x0000 0 sequencer status status [11:0] db_gain 0x000 0 digital gain [12] reserved 0x0 0 reserved [13] reserved 0x0 0 reserved 58 250 reserved 0x0423 1059 reserved rw [4:0] reserved 0x03 3 reserved [9:5] reserved 0x01 1 reserved [14:10] reserved 0x01 1 reserved 59 251 reserved 0x030f 783 reserved rw [7:0] reserved 0xf 15 reserved [15:8] reserved 0x3 3 reserved 60 252 reserved 0x0601 1537 reserved rw [7:0] reserved 0x1 1 reserved [15:8] reserved 0x6 6 reserved 61 253 reserved 0x0000 0 reserved rw [7:0] reserved 0x00 0 reserved [15:8] reserved 0x00 0 reserved 62 254 reserved 0x0000 0 reserved rw [12:0] reserved 0x0000 0 reserved 63 255 reserved 0x0000 0 reserved rw [12:0] reserved 0x0000 0 reserved sequencer roi 256 0 256 roi0_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 1 257 roi0_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 2 258 roi0_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 3 259 roi1_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 4 260 roi1_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 5 261 roi1_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 6 262 roi2_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 7 263 roi2_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 8 264 roi2_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 9 265 roi3_configuration0 0x4f00 20224 roi configuration rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 67 table 30. register map category type description default default (hex) register name bit field address address offset block offset [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 10 266 roi3_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 11 267 roi3_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 12 268 roi4_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 13 269 roi4_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 14 270 roi4_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 15 271 roi5_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 16 272 roi5_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 17 273 roi5_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 18 274 roi6_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 19 275 roi6_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 20 276 roi6_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 21 277 roi7_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 22 278 roi7_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 23 279 roi7_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 24 280 roi8_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 25 281 roi8_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 26 282 roi8_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 27 283 roi9_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 28 284 roi9_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 29 285 roi9_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 68 table 30. register map category type description default default (hex) register name bit field address address offset block offset 30 286 roi10_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 31 287 roi10_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 32 288 roi10_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 33 289 roi11_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 34 290 roi11_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 35 291 roi11_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 36 292 roi12_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 37 293 roi12_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 38 294 roi12_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 39 295 roi13_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 40 296 roi13_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 41 297 roi13_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 42 298 roi14_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 43 299 roi14_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 44 300 roi14_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 45 301 roi15_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 46 302 roi15_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 47 303 roi15_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 48 304 roi16_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 49 305 roi16_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 50 306 roi16_configuration2 0x13ff 5119 roi configuration rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 69 table 30. register map category type description default default (hex) register name bit field address address offset block offset [12:0] y_end 0x13ff 5119 y end configuration 51 307 roi17_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 52 308 roi17_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 53 309 roi17_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 54 310 roi18_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 55 311 roi18_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 56 312 roi18_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 57 313 roi19_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 58 314 roi19_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 59 315 roi19_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 60 316 roi20_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 61 317 roi20_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 62 318 roi20_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 63 319 roi21_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 64 320 roi21_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 65 321 roi21_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 66 322 roi22_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 67 323 roi22_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 68 324 roi22_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 69 325 roi23_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 70 326 roi23_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 70 table 30. register map category type description default default (hex) register name bit field address address offset block offset 71 327 roi23_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 72 328 roi24_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 73 329 roi24_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 74 330 roi24_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 75 331 roi25_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 76 332 roi25_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 77 333 roi25_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 78 334 roi26_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 79 335 roi26_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 80 336 roi26_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 81 337 roi27_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 82 338 roi27_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 83 339 roi27_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 84 340 roi28_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 85 341 roi28_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 86 342 roi28_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 87 343 roi29_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 88 344 roi29_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 89 345 roi29_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 90 346 roi30_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 91 347 roi30_configuration1 0x0000 0 roi configuration rw
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 71 table 30. register map category type description default default (hex) register name bit field address address offset block offset [12:0] y_start 0x0000 0 y start configuration 92 348 roi30_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 93 349 roi31_configuration0 0x4f00 20224 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x4f 79 x end configuration 94 350 roi31_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 95 351 roi31_configuration2 0x13ff 5119 roi configuration rw [12:0] y_end 0x13ff 5119 y end configuration 384 0 384 reserved reserved rw [15:0] reserved reserved ? ? ? ? ? ? 127 511 reserved [15:0] reserved reserved
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 72 package information pin description refer to electrical specifications on page 4 for power supplies and references. the cmos io follow the jedec standard (jedec?jesd8c?01). table 31. pin description pin no. name type direction description a01 vddd_18 supply digital supply - 1.8 v domain a02 mbs2_out analog out for test purposes only. do not connect a03 adc_dout1 cmos out for test purposes only. do not connect a04 gnd_colbias ground column biasing ground - connect to ground a05 gnd_colbias ground column biasing ground - connect to ground a06 vdda_33 supply analog supply - 3.3 v domain a07 vdda_33 supply analog supply - 3.3 v domain a08 vdda_33 supply analog supply - 3.3 v domain a09 vdda_33 supply analog supply - 3.3 v domain a10 vdda_33 supply analog supply - 3.3 v domain a11 vdda_33 supply analog supply - 3.3 v domain a12 vdda_33 supply analog supply - 3.3 v domain a13 vdda_33 supply analog supply - 3.3 v domain a14 vdda_33 supply analog supply - 3.3 v domain a15 vdda_33 supply analog supply - 3.3 v domain a16 vdda_33 supply analog supply - 3.3 v domain a17 vdda_33 supply analog supply - 3.3 v domain a18 vdda_33 supply analog supply - 3.3 v domain a19 vdda_33 supply analog supply - 3.3 v domain a20 vdda_33 supply analog supply - 3.3 v domain a21 vdda_33 supply analog supply - 3.3 v domain a22 vdda_33 supply analog supply - 3.3 v domain a23 vdda_33 supply analog supply - 3.3 v domain a24 vddd_18 supply digital supply - 1.8 v domain a25 vddd_18 supply digital supply - 1.8 v domain b01 vddd_33 supply digital supply - 3.3 v domain b02 ibias_master analog in/out bias reference - connect with 47 k to ibias_out b03 adc_dout2 cmos out for test purposes only. do not connect b04 gnd_colbias ground column biasing ground - connect to ground b05 doutn30 lvds out lvds data out negative - channel 30 b06 doutp28 lvds out lvds data out positive - channel 28 b07 doutn27 lvds out lvds data out negative - channel 27 b08 doutn25 lvds out lvds data out negative - channel 25 b09 doutn23 lvds out lvds data out negative - channel 23 b10 doutn21 lvds out lvds data out negative - channel 21 b11 doutn19 lvds out lvds data out negative - channel 19 b12 doutp17 lvds out lvds data out positive - channel 17 b13 doutn16 lvds out lvds data out negative - channel 16
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 73 table 31. pin description pin no. description direction type name b14 doutn14 lvds out lvds data out negative - channel 14 b15 doutp12 lvds out lvds data out positive - channel 12 b16 doutp10 lvds out lvds data out positive - channel 10 b17 doutp8 lvds out lvds data out positive - channel 8 b18 doutp6 lvds out lvds data out positive - channel 6 b19 doutp4 lvds out lvds data out positive - channel 4 b20 doutn3 lvds out lvds data out negative - channel 3 b21 doutp1 lvds out lvds data out positive - channel 1 b22 gnd_colbias ground column biasing ground - connect to ground b23 clock_inp lvds in lvds clock in positive b24 clock_inn lvds in lvds clock in negative b25 vddd_33 supply digital supply - 3.3 v domain c01 vddd_33 supply digital supply - 3.3 v domain c02 ibias_out analog in/out bias ground reference - connect with 47 k to ibias_master c03 adc_dout9 cmos out for test purposes only. do not connect c04 gnd_colbias ground column biasing ground - connect to ground c05 doutp30 lvds out lvds data out positive - channel 30 c06 doutn28 lvds out lvds data out negative - channel 28 c07 doutp27 lvds out lvds data out positive - channel 27 c08 doutp25 lvds out lvds data out positive - channel 25 c09 doutp23 lvds out lvds data out positive - channel 23 c10 doutp21 lvds out lvds data out positive - channel 21 c11 doutp19 lvds out lvds data out positive - channel 19 c12 doutn17 lvds out lvds data out negative - channel 17 c13 doutp16 lvds out lvds data out positive - channel 16 c14 doutp14 lvds out lvds data out positive - channel 14 c15 doutn12 lvds out lvds data out negative - channel 12 c16 doutn10 lvds out lvds data out negative - channel 10 c17 doutn8 lvds out lvds data out negative - channel 8 c18 doutn6 lvds out lvds data out negative - channel 6 c19 doutn4 lvds out lvds data out negative - channel 4 c20 doutp3 lvds out lvds data out positive - channel 3 c21 doutn1 lvds out lvds data out negative - channel 1 c22 gnd_colbias ground column biasing ground - connect to ground c23 gnd_colbias ground column biasing ground - connect to ground c24 gnd_colbias ground column biasing ground - connect to ground c25 vddd_33 supply digital supply - 3.3 v domain d01 mbs1_out analog out for test purposes only. do not connect d02 adc_dout5 cmos out for test purposes only. do not connect d03 adc_dout10 cmos out for test purposes only. do not connect d04 gnd_colbias ground column biasing ground - connect to ground
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 74 table 31. pin description pin no. description direction type name d05 clock_outp lvds out lvds clock out positive d06 doutn31 lvds out lvds data out negative - channel 31 d07 doutn29 lvds out lvds data out negative - channel 29 d08 doutn26 lvds out lvds data out negative - channel 26 d09 doutn24 lvds out lvds data out negative - channel 24 d10 doutn22 lvds out lvds data out negative - channel 22 d11 doutn20 lvds out lvds data out negative - channel 20 d12 doutn18 lvds out lvds data out negative - channel 18 d13 doutp15 lvds out lvds data out positive - channel 15 d14 doutp13 lvds out lvds data out positive - channel 13 d15 doutp11 lvds out lvds data out positive - channel 11 d16 doutp9 lvds out lvds data out positive - channel 9 d17 doutp7 lvds out lvds data out positive - channel 7 d18 doutp5 lvds out lvds data out positive - channel 5 d19 doutp2 lvds out lvds data out positive - channel 2 d20 doutp0 lvds out lvds data out positive - channel 0 d21 syncp lvds out lvds sync positive d22 gnd_colbias ground column biasing ground - connect to ground d23 miso cmos out spi master in -slave out d24 mosi cmos in spi master out - slave in d25 ss_n cmos in spi slave select (active low) e01 adc_dout0 cmos out for test purposes only. do not connect e02 adc_dout4 cmos out for test purposes only. do not connect e03 srd2_n analog not connected e04 gnd_colbias ground column biasing ground - connect to ground e05 clock_outn lvds out lvds clock out negative e06 doutp31 lvds out lvds data out positive - channel 31 e07 doutp29 lvds out lvds data out positive - channel 29 e08 doutp26 lvds out lvds data out positive - channel 26 e09 doutp24 lvds out lvds data out positive - channel 24 e10 doutp22 lvds out lvds data out positive - channel 22 e11 doutp20 lvds out lvds data out positive - channel 20 e12 doutp18 lvds out lvds data out positive - channel 18 e13 doutn15 lvds out lvds data out negative - channel 15 e14 doutn13 lvds out lvds data out negative - channel 13 e15 doutn11 lvds out lvds data out negative - channel 11 e16 doutn9 lvds out lvds data out negative - channel 9 e17 doutn7 lvds out lvds data out negative - channel 7 e18 doutn5 lvds out lvds data out negative - channel 5 e19 doutn2 lvds out lvds data out negative - channel 2 e20 doutn0 lvds out lvds data out negative - channel 0 e21 syncn lvds out lvds sync negative
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 75 table 31. pin description pin no. description direction type name e22 gnd_colbias ground column biasing ground - connect to ground e23 trigger cmos in trigger e24 sck cmos in spi clock e25 reset_n cmos in active low system reset f01 adc_dout3 cmos out for test purposes only. do not connect f02 adc_dout6 cmos out for test purposes only. do not connect f03 srd2_nguard analog not connected f04 gnd_colbias ground column biasing ground - connect to ground f05 gnd_colbias ground column biasing ground - connect to ground f06 gnd_colbias ground column biasing ground - connect to ground f07 gnd_colbias ground column biasing ground - connect to ground f08 gnd_colbias ground column biasing ground - connect to ground f09 gnd_colbias ground column biasing ground - connect to ground f10 gnd_colbias ground column biasing ground - connect to ground f11 gnd_colbias ground column biasing ground - connect to ground f12 gnd_colbias ground column biasing ground - connect to ground f13 gnd_colbias ground column biasing ground - connect to ground f14 gnd_colbias ground column biasing ground - connect to ground f15 gnd_colbias ground column biasing ground - connect to ground f16 gnd_colbias ground column biasing ground - connect to ground f17 gnd_colbias ground column biasing ground - connect to ground f18 gnd_colbias ground column biasing ground - connect to ground f19 gnd_colbias ground column biasing ground - connect to ground f20 gnd_colbias ground column biasing ground - connect to ground f21 gnd_colbias ground column biasing ground - connect to ground f22 gnd_colbias ground column biasing ground - connect to ground f23 scan_in2 cmos in scan chain input #2 - connect to ground f24 muxmode1 cmos in selects number of output channels f25 muxmode0 cmos in selects number of output channels g01 adc_dout8 cmos out for test purposes only. do not connect g02 adc_dout7 cmos out for test purposes only. do not connect g03 afe_clk cmos out for test purposes only. do not connect g04 srd1_nguard analog not connected g05 srd1_n analog not connected g06 td_anode analog in/out temperature diode - anode g07 td_cathode analog in/out temperature diode - cathode g08 mbs3_in analog in analog test input - connect to ground g09 mbs4_in analog in analog test input - connect to ground g10 spare_ana analog out for test purposes only. do not connect g11 spare_ana analog out for test purposes only. do not connect g12 spare_dig_in cmos in digital test input - connect to ground g13 spare_dig_in cmos in digital test input - connect to ground
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 76 table 31. pin description pin no. description direction type name g14 spare_dig_in cmos in digital test input - connect to ground g15 gnd_colbias ground column biasing ground - connect to ground g16 gnd_colbias ground column biasing ground - connect to ground g17 gnd_colbias ground column biasing ground - connect to ground g18 gnd_colbias ground column biasing ground - connect to ground g19 gnd_colbias ground column biasing ground - connect to ground g20 gnd_colbias ground column biasing ground - connect to ground g21 gnd_colbias ground column biasing ground - connect to ground g22 scan_clk cmos in scan chain clock - connect to ground g23 monitor2 cmos out monitor output #2 g24 monitor1 cmos out monitor output #1 g25 monitor0 cmos out monitor output #0 h21 test_enable cmos in test enable - connect to ground h22 adc_mode cmos in connect to gndd_33 (?0?) h23 spare_dig_out cmos not connected h24 spare_dig_out cmos not connected h25 spare_dig_out cmos not connected j01 spare_vref6t_hv analog not connected j02 spare_vref6t_hv analog not connected j03 spare_vref6t_hv analog not connected j04 spare_vref6t_hv analog not connected j05 gndd_33 ground digital ground - 3.3 v domain j06 gndd_33 ground digital ground - 3.3 v domain j07 gndd_33 ground digital ground - 3.3 v domain j08 gndd_33 ground digital ground - 3.3 v domain j09 gndd_33 ground digital ground - 3.3 v domain j10 gndd_33 ground digital ground - 3.3 v domain j11 gndd_33 ground digital ground - 3.3 v domain j12 gndd_33 ground digital ground - 3.3 v domain j13 gndd_18 ground digital ground - 1.8 v domain j14 gndd_18 ground digital ground - 1.8 v domain j15 gndd_18 ground digital ground - 1.8 v domain j16 gndd_18 ground digital ground - 1.8 v domain j17 gndd_18 ground digital ground - 1.8 v domain j18 gndd_18 ground digital ground - 1.8 v domain j19 gndd_18 ground digital ground - 1.8 v domain j20 gndd_18 ground digital ground - 1.8 v domain j21 gndd_18 ground digital ground - 1.8 v domain j22 gnd_calib ground pixel calibration ground - connect to ground j23 gnd_trans supply pixel transfer ground - sinking supply j24 gnd_resfd ground floating diffusion reset ground - connect to ground j25 gnd_resfd ground floating diffusion reset ground - connect to ground
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 77 table 31. pin description pin no. description direction type name k01 spare_vref6t analog not connected k02 spare_vref6t analog not connected k03 spare_vref6t analog not connected k04 spare_vref6t analog not connected k05 spare_vref6t analog not connected k06 spare_vref6t analog not connected k07 spare_vref6t analog not connected k08 spare_vref6t analog not connected k9 vdd_pix supply pixel array supply k10 vdd_pix supply pixel array supply k11 vdd_pix supply pixel array supply k12 vdd_pix supply pixel array supply k13 vdd_pix supply pixel array supply k14 vdd_pix supply pixel array supply k15 vdd_pix supply pixel array supply k16 vdd_pix supply pixel array supply k17 gnd_sel ground pixel select ground - connect to ground k18 gnd_sel ground pixel select ground - connect to ground k19 gnd_sel ground pixel select ground - connect to ground k20 gnd_sel ground pixel select ground - connect to ground k21 vdd_calib supply pixel calibration supply k22 gnd_calib ground pixel calibration ground - connect to ground k23 gnd_trans supply pixel transfer ground - sinking supply k24 gnd_resfd ground floating diffusion reset ground - connect to ground k25 gnd_resfd ground floating diffusion reset ground - connect to ground l01 vref_colmux supply column multiplexer reference supply l02 vdd_pix supply pixel array supply l03 vdd_pix supply pixel array supply l04 vdd_pix supply pixel array supply l05 vdd_pix supply pixel array supply l06 vdd_pix supply pixel array supply l07 vdd_pix supply pixel array supply l08 vdd_pix supply pixel array supply l09 vdd_pix supply pixel array supply l10 vdd_pix supply pixel array supply l11 vdd_pix supply pixel array supply l12 vdd_pix supply pixel array supply l13 vdd_pix supply pixel array supply l14 vdd_pix supply pixel array supply l15 vdd_pix supply pixel array supply l16 vdd_pix supply pixel array supply l17 vdd_casc supply cascode supply
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 78 table 31. pin description pin no. description direction type name l18 vdd_casc supply cascode supply l19 vdd_sel supply pixel select supply l20 vdd_sel supply pixel select supply l21 vdd_calib supply pixel calibration supply l22 gnd_calib ground pixel calibration ground - connect to ground l23 gnd_trans supply pixel transfer ground - sinking supply l24 vdd_resfd supply floating diffusion reset supply l25 vref_colmux supply column multiplexer reference supply m01 vref_colmux supply column multiplexer reference supply m02 vdd_pix supply pixel array supply m03 vdd_pix supply pixel array supply m04 vdd_pix supply pixel array supply m05 vdd_pix supply pixel array supply m06 vdd_pix supply pixel array supply m07 vdd_pix supply pixel array supply m08 vdd_pix supply pixel array supply m09 vdd_pix supply pixel array supply m10 vdd_pix supply pixel array supply m11 vdd_pix supply pixel array supply m12 vdd_pix supply pixel array supply m13 vdd_pix supply pixel array supply m14 vdd_pix supply pixel array supply m15 vdd_pix supply pixel array supply m16 vdd_pix supply pixel array supply m17 vdd_casc supply cascode supply m18 vdd_casc supply cascode supply m19 vdd_sel supply pixel select supply m20 vdd_sel supply pixel select supply m21 vdd_calib supply pixel calibration supply m22 gnd_calib ground pixel calibration ground - connect to ground m23 gnd_trans supply pixel transfer ground - sinking supply m24 vdd_resfd supply floating diffusion reset supply m25 vref_colmux supply column multiplexer reference supply n01 vddd_33 supply digital supply - 3.3-v domain n02 vdd_pix supply pixel array supply n03 gnd_colpc ground column precharge ground - connect to ground n04 gnd_colpc ground column precharge ground - connect to ground n05 gnd_colpc ground column precharge ground - connect to ground n06 gnd_colpc ground column precharge ground - connect to ground n07 gnd_colpc ground column precharge ground - connect to ground n08 gnd_colpc ground column precharge ground - connect to ground n09 gnd_colpc ground column precharge ground - connect to ground
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 79 table 31. pin description pin no. description direction type name n10 gnd_colpc ground column precharge ground - connect to ground n11 gnd_colpc ground column precharge ground - connect to ground n12 gnd_colpc ground column precharge ground - connect to ground n13 gnd_colpc ground column precharge ground - connect to ground n14 gnd_colpc ground column precharge ground - connect to ground n15 gnd_colpc ground column precharge ground - connect to ground n16 gnd_colpc ground column precharge ground - connect to ground n17 gnd_colpc ground column precharge ground - connect to ground n18 gnd_colpc ground column precharge ground - connect to ground n19 gnd_colpc ground column precharge ground - connect to ground n20 gnd_colpc ground column precharge ground - connect to ground n21 vdd_calib supply pixel calibration supply n22 vdd_trans supply pixel transfer supply n23 vdd_trans supply pixel transfer supply n24 vdd_resfd supply floating diffusion reset supply n25 vddd_33 supply digital supply - 3.3 v domain p01 vddd_33 supply digital supply - 3.3 v domain p02 vdd_pix supply pixel array supply p03 gnd_colpc ground column precharge ground - connect to ground p04 gnd_colpc ground column precharge ground - connect to ground p05 gnd_colpc ground column precharge ground - connect to ground p06 gnd_colpc ground column precharge ground - connect to ground p07 gnd_colpc ground column precharge ground - connect to ground p08 gnd_colpc ground column precharge ground - connect to ground p09 gnd_colpc ground column precharge ground - connect to ground p10 gnd_colpc ground column precharge ground - connect to ground p11 gnd_colpc ground column precharge ground - connect to ground p12 gnd_colpc ground column precharge ground - connect to ground p13 gnd_colpc ground column precharge ground - connect to ground p14 gnd_colpc ground column precharge ground - connect to ground p15 gnd_colpc ground column precharge ground - connect to ground p16 gnd_colpc ground column precharge ground - connect to ground p17 gnd_colpc ground column precharge ground - connect to ground p18 gnd_colpc ground column precharge ground - connect to ground p19 gnd_colpc ground column precharge ground - connect to ground p20 gnd_colpc ground column precharge ground - connect to ground p21 gnd_colpc ground column precharge ground - connect to ground p22 vdd_trans supply pixel transfer supply p23 vdd_trans supply pixel transfer supply p24 vdd_resfd supply floating diffusion reset supply p25 vddd_33 supply digital supply - 3.3 v domain r01 vddd_18 supply digital supply - 1.8 v domain
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 80 table 31. pin description pin no. description direction type name r02 vddd_18 supply digital supply - 1.8 v domain r03 vddd_18 supply digital supply - 1.8 v domain r04 gnd_colpc ground column precharge ground - connect to ground r05 gnda_33 ground analog ground - 3.3 v domain r06 gnda_33 ground analog ground - 3.3 v domain r07 gnda_33 ground analog ground - 3.3 v domain r08 gnda_33 ground analog ground - 3.3 v domain r09 gnda_33 ground analog ground - 3.3 v domain r10 gnda_33 ground analog ground - 3.3 v domain r11 gnda_33 ground analog ground - 3.3 v domain r12 gnda_33 ground analog ground - 3.3 v domain r13 gnda_33 ground analog ground - 3.3 v domain r14 gnda_33 ground analog ground - 3.3 v domain r15 gnda_33 ground analog ground - 3.3 v domain r16 gnda_33 ground analog ground - 3.3 v domain r17 gnda_33 ground analog ground - 3.3 v domain r18 gnda_33 ground analog ground - 3.3 v domain r19 gnda_33 ground analog ground - 3.3 v domain r20 gnda_33 ground analog ground - 3.3 v domain r21 gnda_33 ground analog ground - 3.3 v domain r22 gnda_33 ground analog ground - 3.3 v domain r23 vddd_18 supply digital supply - 1.8 v domain r24 vddd_18 supply digital supply - 1.8 v domain r25 vddd_18 supply digital supply - 1.8 v domain
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 81 mechanical specifications table 32. mechanical specifications parameter description min typ max units die die thickness 725 m die size 25.5 x 32.5 mm 2 die center, x offset to the center of package -50 0 50 m die center, y offset to the center of the package -50 0 50 m die position, tilt to the die attach plane ?1 0 1 deg die rotation accuracy (referenced to die scribe and lead fingers on package on all four sides) ?1 0 1 deg optical center referenced from the die/package center (x-dir) 0 m optical center referenced from the die/package center (y-dir) 3602 m distance from bottom of the package to top of the die surface 1.605 1.80 1.995 mm distance from top of the die surface to top of the glass lid 1.075 1.45 1.855 mm glass lid specification xy size 32.47 x 39.4 mm 2 thickness 0.7 mm spectral response range 400 1000 nm transmission of glass lid (refer to figure 44) 92 % glass lid material d263 teco (no coatings on glass) mechanical shock jesd22-b104c; condition g 2000 g vibration jesd22-b103b; condition 1 2000 hz mounting profile pb?free wave soldering profile for pin grid array package recommended socket andon electronics corporation ( www.andonelectronics.com ) 10?31?13a?355?400t4?r27?l14 note: optical center min/max tolerance is calculated on x/y package tolerances with package center as a reference.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 82 package drawing figure 49. python xk package diagram all dimensions are in mm, unless specified otherwise.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 83 optical center information the center of the die (cd) is the center of the cavity the center of the die (cd) is exactly at 50% between the outsides of the two outer seal rings the center of the cavity is exactly at 50% between the insides of the finger pads. ? die outer dimensions: ? b4 is the reference for the die (0,0) in m ? b1 is at (0,32500) m ? b2 is at (25500,32500) m ? b3 is at (25500,0) m ? active area outer dimensions ? a1 is the at (1214, 31388) m ? a2 is at (24286, 31388) m ? a3 is at (24286, 8316) m ? a4 is at (1214, 8316) m ? center of the active area ? aa is at (12750, 19852) m ? center of the die ? cd is at (12750, 16250) m note: the data represented here is for the 25k variant. for the other variants only a1?a4 are different. centers remain the same. figure 50. graphical representation of the optical center
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 84 glass lid the python xk image sensor uses a glass lid without any coatings. figure 51 shows the transmission characteristics of the glass lid. as seen in figure 51, the sensor does not have an infrared attenuating filter glass. a filter must be provided in the optical path when color devices are used (source: http://www.pgo-online.com ). figure 51. transmission characteristics of glass lid specifications and useful references specifications, application notes and useful resources can be accessible via customer login account at myon - isg extranet. https://www.onsemi.com/powersolutions/myon/ercispfol der.do useful references for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note ( an52561/d ) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook ( hbd851/d ) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com . application note and references ? python xk layout dsn drawing ? python xk 3d package stp file for cad acceptance criteria specification the product acceptance criteria is available on request. this document contains the criteria to which the python xk is tested prior to being shipped. return material authorization (rma) refer to the on semiconductor rma policy procedure at http://www.onsemi.com/site/pdf/cat_returns_failurean alysis.pdf
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 85 acronyms acronym description adc analog-to-digital converter afe analog front end bl black pixel data cdm charged device model cds correlated double sampling cmos complementary metal oxide semiconductor crc cyclic redundancy check dac digital-to-analog converter ddr double data rate dnl differential non-llinearity ds double sampling eia electronic industries alliance esd electrostatic discharge fe frame end fot frame overhead time fpga field programmable gate array fpn fixed pattern noise fps frame per second fs frame start hbm human body model img image data (regular pixel data) inl integral non-linearity ip intellectual property acronym description le line end ls line start lsb least significant bit lvds low-voltage differential signaling msb most significant bit pga programmable gain amplifier pls parasitic light sensitivity prbs pseudo-random binary sequence prnu photo response non-uniformity qe quantum efficiency rgb red-green-blue rma return material authorization rms root mean square roi region of interest rot row overhead time s/h sample and hold snr signal-to-noise ratio spi serial peripheral interface tia telecommunications industry association t j junction temperature tr training pattern % rh percent relative humidity
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 86 glossary conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. conversion gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. cds correlated double sampling. this is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light. cfa color filter array. the materials deposited on top of pixels that selectively transmit color. dnl differential non-linearity (for adcs) dsnu dark signal non-uniformity. this parameter characterizes the degree of non-uniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. inl integral nonlinearity (for adcs) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixel array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response non-uniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and converting them into electrons. it is photon wavelength and pixel color dependent. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. ?soft? reset occurs when the reset transistor is operated below the threshold. ?hard? reset occurs when the reset transistor is oper- ated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodi- ode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wave- length. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux is equal to 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels.
noip1sn025ka, noip1sn016ka, noip1sn012ka, noip1sn010ka www.onsemi.com 87 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 noip1sn025ka/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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